• Title/Summary/Keyword: Standard Operation Time

Search Result 646, Processing Time 0.031 seconds

Radiologic assessment of bone healing after orthognathic surgery using fractal analysis

  • Park Kwan-Soo;Heo Min-Suk;Lee Sam-Sun;Choi Soon-Chul;Park Tae-Won;Jeon In-Seong;Kim Jong-Dae
    • Imaging Science in Dentistry
    • /
    • v.32 no.4
    • /
    • pp.201-206
    • /
    • 2002
  • Purpose : To evaluate the radiographic change of operation sites after orthognathic surgery using the digital image processing and fractal analysis. Materials and Methods : A series of panoramic radiographs of thirty-five randomly selected patients who had undergone mandibular orthognathic surgery (bilateral sagittal split ramus osteotomy) without clinical complication for osseous healing, were taken. The panoramic radiographs of each selected patient were taken at pre-operation (stage 0), 1 or 2 days after operation (stage 1), 1 month after operation (stage 2), 6 months after operation (stage 3), and 12 months after operation (stage 4). The radiographs were digitized at 600 dpi, 8 bit, and 256 gray levels. The region of interest, centered on the bony gap area of the operation site, was selected and the fractal dimension was calculated by using the tile-counting method. The mean values and standard deviations of fractal dimension for each stage were calculated and the differences among stage 0, 1, 2, 3, and 4 were evaluated through repeated measures of the ANOVA and paired t-test. Results : The mean values and standard deviations of the fractal dimensions obtained from stage 0, 1, 2, 3, and 4 were 1.658±0.048, 1.580±0.050, 1.607±0.046, 1.624±0.049, and 1.641 ±0.061, respectively. The fractal dimensions from stage 1 to stage 4 were shown to have a tendency to increase (p < 0.05). Conclusion: The tendency of the fractal dimesion to increase relative to healing time may be a useful means of evaluating post-operative bony healing of the osteotomy site.

  • PDF

Generation of Cavity and Core Plates of an Injection Mold for a Pseudo-Solid Part Model (의사 솔리드 모델의 캐비티 및 코어판 생성)

  • 장진우;이상헌;임성락
    • Proceedings of the Korean Society of Precision Engineering Conference
    • /
    • 2003.06a
    • /
    • pp.1601-1604
    • /
    • 2003
  • This paper describes a split operation for generation of core and cavity plates of an injection mold for a pseudo-solid model of a plastic part. Here, a pseudo-solid model means a sheet model that looks like a solid model. but whose boundary is not closed. When a solid model created in a different CAD system is imported through standard data exchange format, a pseudo-solid model is created in most cases as tolerance or some other problems make sewing operation failed. As most existing mold design system based on solid modeling kernels require a complete part solid model, mold designers have to do time-consuming healing operations to convert a pseudo-solid to solid. The essential capability of mold design system is the split operation for generation of core and cavity plates. Thus. we developed a split operation for pseudo-solid part model to eliminate or reduce healing preprocessing for mold design.

  • PDF

Design of a microprocessor control system for an one-through tube boiler using RTE (RTE(Real Time Executive)를 이용한 수관식 관류 보일러 제어 시스템의 설계)

  • 김정호;한동원;조삼현
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 1986.10a
    • /
    • pp.225-231
    • /
    • 1986
  • A design of an industrial microcomputer control system for an one-through tube boiler using oil is presented. The microcomputer system is based on standard iSBC 88/40 board. The software consist of a RTE(real time executive) and application tasks. The designed control system saves fuel and gives a more reliable over-all operation.

  • PDF

The Communication Method at the Auto-Startup System using TCP/IP and VXI and Expert System(G2)

  • Kim, Jung-Soo;Joon Lyon
    • Transactions on Control, Automation and Systems Engineering
    • /
    • v.1 no.2
    • /
    • pp.141-146
    • /
    • 1999
  • This paper describes the communication method of an auto-startup system. The Auto-Startup system is designed to operate a nuclear power plant automatically during the startup operation . In general , the operations during startup in existing plant have only been manually controlled by the operator. The manual operation caused to the operator mistake. The Auto-Startup system consists of the Distributed Control System(DCS) and G2 (Expert System). Also, Functional Test Facility(FTF) provides the plant's real-data for an Auto-Startup system. So, it is necessary to develop the communication method between these systems. We developed two methods ; one is a network and the other is a hardwire line. To communicate between these systems (DCS-G2 and DCS-FTF) , we developed the communication program. In case of DCS-FTF, we used the TCP/IP and VXI. BUt, in case of DCS-G2 , we , what it called , developed the bridge program using the GSI(G2 Standard Interface). We test to check the function of the important parameter, in time, for analysis of the developed communication method. The results are a good performance when we check the communication time of important parameter. We conclude that Auto-startup system could save heat-up time about at least 5 hours and reduced the change of the reactor operation and trip.

  • PDF

Design and Implementation of Simulator for Link-16 Network Operational Performance Analysis (Link-16 네트워크 운용성능분석을 위한 시뮬레이터 설계 및 구현)

  • Lee, Sangtae;Wi, Sounghyouk;Kim, Youngseung;Lee, Jungsik;Jee, Seungbae;Lee, Seungchan
    • Journal of the Korea Society for Simulation
    • /
    • v.28 no.4
    • /
    • pp.33-43
    • /
    • 2019
  • Link-16 is a data link that provides joint interoperability to the US Navy, Air Force and NATO. Currently, the military relies entirely on foreign SW and tools for test environment, tactical simulation training and interoperability verification test for Link-16 operation. Therefore, it is necessary to develop Link-16 based operation environment test tool. In this paper, Link-16 network operational performance analysis simulator was developed by analyzing the function of Link-16 foreign tools. It also implements the SIMPLE standard interface for interworking with foreign SW and tools. The functional model for Link-16 network operation performance analysis consists of pre-analysis, real-time operational analysis, and post-analysis functional model. Each functional model test was performed through SIMPLE interworking with foreign SW and tools. Link-16 network operation performance analysis If we replace foreign SW through simulator, we can perform tactical training, network design verification and operation (scenario) verification for our military.

An H.264 Video Decoder which Guarantees Real-Time Operation with Minimum Degradation (최소의 화질 열화가 함께 실시간 동작이 보장되는 H.264 동영상 복호기)

  • Kim, Jong-Chan;Kim, Du-Ri;Lee, Dong-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.33 no.10C
    • /
    • pp.805-812
    • /
    • 2008
  • H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

A Holistic Approach to Optimizing the Lifetime of IEEE 802.15.4/ZigBee Networks with a Deterministic Guarantee of Real-Time Flows

  • Kim, Kang-Wook;Park, Myung-Gon;Han, Junghee;Lee, Chang-Gun
    • Journal of Computing Science and Engineering
    • /
    • v.9 no.2
    • /
    • pp.83-97
    • /
    • 2015
  • IEEE 802.15.4 is a global standard designed for emerging applications in low-rate wireless personal area networks (LR-WPANs). The standard provides beneficial features, such as a beacon-enabled mode and guaranteed time slots for realtime data delivery. However, how to optimally operate those features is still an open issue. For the optimal operation of the features, this paper proposes a holistic optimization method that jointly optimizes three cross-related problems: cluster-tree construction, nodes' power configuration, and duty-cycle scheduling. Our holistic optimization method provides a solution for those problems so that all the real-time packets can be delivered within their deadlines in the most energy-efficient way. Our simulation study shows that compared to existing methods, our holistic optimization can guarantee the on-time delivery of all real-time packets while significantly saving energy, consequently, significantly increasing the lifetime of the network. Furthermore, we show that our holistic optimization can be extended to take advantage of the spatial reuse of a radio frequency resource among long distance nodes and, hence, significantly increase the entire network capacity.

Comparison of the Operational Speed of Hard-wired and IEC 61850 Standard-based Implementations of a Reverse Blocking Protection Scheme

  • Mnguni, Mkhululi Elvis Siyanda;Tzoneva, Raynitchka
    • Journal of Electrical Engineering and Technology
    • /
    • v.10 no.3
    • /
    • pp.740-754
    • /
    • 2015
  • This paper focuses on the reverse blocking busbar protection scheme with aim to improve the speed of its operation and at the same time to increase operational reliability, flexibility and stability of the protection during external and internal faults by implementation of the extended functionality provided by the IEC61850 standard-based protective Intelligent Electronic Devices (IEDs). The practical implementation of the scheme by the use of IEC 61850 standard communication protocol is investigated. The proposed scheme is designed for a radial type of a distribution network and is modeled and simulated in the DigSILENT software environment for various faults on the busbar and its outgoing feeders. A laboratory test bench is built using three ABB IEDs 670 series that are compliant with the IEC 61850 standard, CMC 356 Omicron test injection device, PC, MOXA switch, and a DC power supplier. Two types of the reverse blocking signals between the IEDs in the test bench are considered: hard wired and Ethernet communication by using IEC 61850 standard GOOSE messages. Comparative experimental study of the operational trip response speeds of the two implementations for various traffic conditions of the communication network shows that the performance of the protection scheme for the case of Ethernet IEC 61850 standard-based communication is better.

Improved Circuits for Single-photon Avalanche Photodiode Detectors

  • Kim, Kyunghoon;Lee, Junan;Song, Bongsub;Burm, Jinwook
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.14 no.6
    • /
    • pp.789-796
    • /
    • 2014
  • A CMOS photo detection bias quenching circuit is developed to be used with single photon avalanche photodiodes (SPADs) operating in Geiger mode for the detection of weak optical signals. The proposed bias quenching circuits for the performance improvement reduce the circuit size as well as improve the performance of the quenching operation. They are fabricated in a $0.18-{\mu}m$ standard CMOS technology to verify the effectiveness of this technique with the chip area of only $300{\mu}m^2$, which is about 60 % of the previous reported circuit. Two types of proposed circuits with resistive and capacitive load demonstrated improved performance of reduced quenching time. With a commercial APD by HAMAMATSU, the dead time can be adjusted as small as 50 ns.

VLSI Design of Cryptographic Processor for SEED and Triple DES Encryption Algorithm (SEED 와 TDES 암호 알고리즘을 구현하는 암호 프로세서의 VLSI 설계)

  • 정진욱;최병윤
    • Proceedings of the IEEK Conference
    • /
    • 2000.06b
    • /
    • pp.169-172
    • /
    • 2000
  • This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

  • PDF