• Journal of IKEEE
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• v.22 no.2
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• pp.506-509
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• 2018

Recently, number of components and operation frequency rapidly increase in automotive systems. This often leads to EMI (electromagnetic interference) where automotive systems suffer from malfunctions induced by electromagnetic wave. This paper surveys various EMC (electromagnetic compatibility) compliance technologies such as EMI filter, EMI shielding materials, and spread spectrum clock generator. Their pros and cons are also explained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1884-1891
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• 2012

In this paper, we design the sliding correlator SS transceiver which supports short message service. We also analyze the PN code acquisition circuit that is essential for spread spectrum receiver. Using Maxplus II tool provided by altera Co., Ltd, we have designed PN code generator, and sliding correlator for PN code acquisition. Then, they have been made into FPGA by way of EPM7064SLC44-10 - a chip of Altera Co., Ltd. Additionally, we have designed delay clock circuit which is faster than the clock of Tx PN clock, designed switching circuit to control the clock rate and data demodulation circuit. The performance of the transceiver is evaluated from the experimental results. Especially, the performance of PN code acquisition accomplished by sliding correlator which is very important to evaluate spread spectrum receiver is evaluated with the comparison of the lock states.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.475-484
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• 1990

This paper proposes a method for the implementation of a power line communication equipment using power line synchronization in a direct-sequence spread spectrum communication system. In order to implement a network using a power line as a transmission channel we have investigated the utilization of direct-sequence speread spctrum which gives such advantages as robustness against narrow-band interference and noise, and realization of multiple access. In a power line, however, complexity of synchronization makes it difficult to realize a multiple access and cost down and system simplification. The proposed technique of power line synchronization makes it possible to get cost down and system size small, and the realization of multiple communication can be achieved by the addition of address setting circuit.

• The Magazine of the IEIE
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• v.21 no.7
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• pp.43-51
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• 1994

본 논문에서는 최근 주목을 받고 있는 대역확산 통신방식을 이용한 무선LAN 시스템의 하드웨어 구현에 관해 논한다. 내용으로는 직접확산 (Direct Sequence Spread Spectrum (DS/SS)) 통신방식을 이용한 무선 LAN 전송부 구조, 디지탈 정합필터를 이용한 역확산 및 비동기 DS/SS 수신기 구조, DBPSK 및 DQPSK 변복조 방식, Timing 및 Clock 복원, 그리고 Carrier Sensing 방식등이 포함된다. 또한 실제 시스템 구현을 위해 필요한 몇가지 변수들에 대해서도 논한다.

• Journal of Satellite, Information and Communications
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• v.4 no.2
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• pp.39-45
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• 2009

This paper proposes the specific code synchronization technique for DS-SS(Direct Sequence-Spread Spectrum transmission in the DVB-RCS +M standard. DS-SS is better than multi-carrier transmission method under nonlinear channel but imposes a long acquisition time. To improve the synchronization aspect, the robust correlation structure is introduced for acquisition and the nonlinear delay lock loop is done for tracking. MAT(Mean Acquisition Time) performances is shown to validate its superiority. In addition, code tracking and jitter performances are done when code tracking algorithm based on 2 oversamples which is not influenced by sampling clock timing offset and carrier freq. offset is used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.1
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• pp.98-107
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• 1998

For implementation of FM-DS/SS system. This paper has analyzed SO(Synchronous Oscillator) being oscillated by the motivation of injected signal. Transmitter has adopted FM-DS/SS modulation method using RF output-signal of FM. Receiver is used SO to demodulation of FM-DS/SS and applied sliding correlator for synchronization of PN clock. As a result of the inspection, SO presented stable lock ability in spite of doppler apperance and proved the synchronous properties of it in the FM-DS/SS system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.417-426
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• 2000

In this paper, CE-CPSK(Constant Envelope Continuous Phase Shift Keying) modulated DS/SS(Direct Sequence Spread Spectrum) transceiver with 908 MHz carrier frequency and 1.5 MHz PN clock rate is proposed. To overcome the effect of nun-linear power amplifier, CE-CPSK modulation method which has the constant envelope and continuous phase characteristics is proposed. To analyze the DS/SS receiver performance with respect to code tracking loop, multipath fading channel is characterized as a two-ray Rayleigh fading channel. To compensate the demerit of analog delay locked loop, digital delay locked loop is employed for code tracking loop. Simulation and experimental examination has been carried out in AWGN(Additive White Gaussian Noise) and Rayleigh fading channel environment in order to prove validity of the proposed method.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.35-43
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• 1998

This study has been experimented the characteristics of synchronous oscillator for clock recovery of Direct Sequence/Spread Spectrum(DS/SS) communication. When external wave is not provided, The Synchronous Oscillator(SO) oscillates at its natural frequency. As soon as external signal is applied, the SO starts tracking the external frequency which can be sinusoidal, pulsed or some other waveform. Thus, the output is synchronized with the range of wide tracking bandwidth to the external frequency Specifically, the SO also posses frequency division and multiplication capability. All of these indicate that the SO can overcome difficulties to get synchronization in coherent digital communication systems. We make a practical application of DS/SS communication with study on the synchronous properties of SO. As the result, we have a good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.871-880
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• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.