• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.391-396
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• 2009

In this paper, a control algorithm for DC-Link voltage unbalancing compensation of a four-switch inverter for a three-phase BLDC motor drive is proposed. Compared with a conventional six-switch inverter, the split source of the four-switch inverter can be obtained by splitting DC-link capacitor into two capacitors to drive the three phase BLDC motor. The voltages across each of two capacitors are not always equal in steady state because of the unbalance in the impedance of the DC-link capacitors $C_1$ and $C_2$ or the variable current flowed into the capacitor's neutral point in motor control. Despite the unbalance, if the BLDC motor may be run for a long time the voltage across one of the capacitors is more increased. So the unbalance in the capacitors voltages will be accelerated. As a result, The current ripple and torque ripple is increased due to the fluctuation of input current which flows into 3-phase BLDC motor. According to that, the vibration of motor will be increased and the whole system will be instable. This paper presents a control algorithm for DC-Link voltage unbalancing compensation. The sampling from the voltages across each of two capacitors is used to perform the voltage control of DC-Link by using the feedforward controller.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.111-112
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• 2013

The three-phase four-leg voltage source inverter (VSI) topology can be an interesting option for the three phase-four wire system. With an additional leg, this topology can handle the neutral current, hence the DC link capacitance can be reduced significantly. In this paper the three dimensional space vector modulation (3D SVM) in ${\alpha}{\beta}{\gamma}$ coordinates for the three-phase four-leg VSI is presented. By using the 3D SVM method, the DC link voltage can be reduced by 16% compared with the split DC link capacitor topology and the output distortion can also be reduced under the unbalanced load condition.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.5
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• pp.352-358
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• 2018

A split-capacitor (SC) dual-active-bridge (DAB) converter is proposed in this study. The DC-link capacitors of input and output are split in the proposed converter. The primary and secondary windings of transformer are connected to the midpoints of the DC-links. Hence, the SC DAB converter can inherently prevent transformer from saturation. Although the switch current stress of the proposed converter is twice that of the conventional DAB converter, the switch voltage stress is reduced by half. Therefore, the proposed converter can reduce switching loss and achieve high efficiency in a high switching frequency. Given the SC structure, the proposed converter can readily be connected to neutral-point-clamped- or half-bridge-type converters. The topology of the proposed converter is presented and the operating principle is analyzed in detail. A 3-kW hardware prototype was built and tested to verify the performance of the proposed converter.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.343-346
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• 2002

In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.2
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• pp.54-61
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• 2015

In 3-phase 4-wire inverter, the unbalanced loads cause to increase the neutral current which brings the voltage deviation between the split dc-link capacitors to be larger. In order to solve this problem, a neutral leg is provided additively to the ordinary inverter circuit and the associated control methods are devised. This paper proposes a new neutral-leg controller based on a PR controller and shows relatively good performance even under unbalanced linear loads and nonlinear loads. The proposed control strategy illustrates its effectiveness under the various operating conditions through simulation works.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.345-350
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• 2014

DC electrolytic capacitor is widely used in the power converter including PWM inverter, switching power supply and PFC Boost converter system because of its large capacitance, small size and low cost. In this paper, basic characteristics of DC electrolytic capacitor vs. frequency is presented and the real-time estimation scheme of ESR and capacitance based on the bandpass filtering is adopted to the single phase boost converter of uninterruptible power supply to diagnose its split dc-link capacitors. The feasibility of this real-time failure prediction monitoring system is verified by the computer simulation of the 5[kW] singe phase PFC half-bridge boost converter.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.109-116
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• 2016

This paper proposes an analytic model for four-switch inverter (FSI)-driven wye (Y) or delta (Δ)-connected motors with a current ripple reduction algorithm. FSIs employ four switches in controlling three-phase load instead of using six switches. They have split dc-link stage, and due to this inherent structure there exists the voltage difference between upper and lower capacitors, which results in distortion of the inverter output voltage. To study characteristics of FSIs, this paper presents an advanced simulation models of FSI-driven control system for 3-phase motor that can has a wire connection either Y or Δ. In addition, this paper introduces a current ripple reduction scheme that mitigates degradation of control performance due to the voltage difference between the dc-link capacitors. The validity of the proposed method and the analytic model is verified by simulations and experiments carried out with 1-HP induction machine with Y or Δ-connection

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.95-96
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• 2017

A three-level inverter is widely used thanks to its excellent performances, but the voltage may fluctuate at the neutral point of the split DC-Link. Neutral point voltage fluctuations cause inverter performance degradation and switching element damage, so the neutral point voltage control is essential. However, the neutral point control can be also limited by modulation index and power factor. This paper analyzes the limitation of the neutral point voltage control due to the limitation of zero-sequence voltage, and suggests a method to determine the region where the PWM has to be changed for a better neutral point control.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.211-212
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• 2012

This paper proposes a single current sensor control technique for controlling motors that use only a single DC-Link current sensing resistor to obtain the information of three line currents. However, the measurement is distorted due to the too narrow current pulse width in the shunt resistor. To solve this problem, the existing phase current reconstruction methods are voltage split methods. They have a disadvantage which makes noise. A new dedicated observer is applied to decrease noise problem. Experimental results showed the effectiveness of the proposed method.