• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.234-238
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• 대한전자공학회논문지TC
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• 제46권1호
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• pp.94-101
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• 2009

본 논문에서는 RF 집적회로 설계를 위한 $0.13{\mu}m$ RF CMOS용 인덕터 라이브러리를 개발하였다. 스케일러블 모델링을 위해 선폭, 회전수, 내경을 조절하여 다수의 인덕터 패턴을 제작하고, 정확한 패드 효과 보상을 위해 급전 구조를 최적화하였다. 제작된 패턴의 S-파라미터 측정 데이터를 이용하여 각 소자별로 이중-$\pi$ 등가회로 소자값을 추출한 뒤 이 값들을 인덕터의 물리적 설계 변수의 함수로 표현하는 스케일러블 모델링을 수행하였다. 개발된 라이브러리는 표준(standard) 구조와 대칭(symmetric) 구조를 가지는 두 종류의 스케일러블 인덕터 모델을 제공하며, 모델 유효 주파수는 30GHz 또는 자기공진주파수까지이다. 표준구조 인덕터의 경우 $0.12{\sim}10.7nH$의 인덕턴스를, 대칭구조 인덕터의 경우는 $0.08{\sim}13.6nH$의 인덕턴스를 갖는다. 본 연구를 통해 최종적으로 10%이하의 오차를 가지는 RF CMOS용 인덕터 라이브러리를 완성하였다.

• 한국산학기술학회논문지
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• 제13권9호
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• pp.4126-4130
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• 2012

본 논문에서는 고주파수 무선 신호 전송을 위한 AC 커플링(Coupling) 기반의 평면 나선형 인덕터를 제안하고, 이에 대한 다양한 구조의 인덕터를 설계, 모델링 및 특성을 분석하였다. 커패시턴스의 의한 영향을 줄이기 위해서는 두 박막 인덕터가 서로 평행하게 위치함으로서 인덕터 간의 커패시턴스를 줄여야 한다. 이를 위해 두 가지 구조를 제안하였다. 첫 번째 구조는 inter-diagonal 구조로 평행한 두 인덕터의 도선 부분이 겹치지 않게 만든 구조이다. 이 구조의 경우 비록 평행하게 겹치지는 않지만 도선의 두께와 폭이 좁으므로 서로 엇갈리는 위치에 도선이 위치하더라도 실제 커패시턴스의 변화가 작아서 전체적인 S-파라미터의 특성이 크게 변하지 않았다. 두 번째 구조는 On-chip형 구조로 두 박막 인덕터가 평행하게 존재하지만 마주보지 않게 사선형으로 배치한 구조이다. 이 구조의 경우 박막 인덕터 간의 수평거리가 길어짐에 따라 두 번에 걸쳐서 일어나는 공진이 한 번으로 줄어드는 것을 볼 수 있는데, 이는 두 인덕터 간의 거리가 멀어짐으로 인해 박막 인덕터 간의 커패시턴스 영향이 점점 줄어들기 때문이다.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2000년도 International Symposium on Magnetics The 2000 Fall Conference
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• pp.532-538
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• 2000

A double rectangular spiral inductor is fabricated using FeTaN films. The inductor is composed of internal coils sandwiched by magnetic layers. Characteristics of inductor performance are investigated with an emphasis on planarization of magnetic films. In the absence of the planarization process, the grating topology of upper magnetic films over coil arrays degrades the soft magnetic properties and the inductor performance. It also induces a longitudinal magnetic anisotropy with the easy axis aligned to the magnetic flux direction. This alignment prevents the upper magnetic films from contributing to the total induction. Glass bonding is a viable method for achieving a completely planar inductor structure. The planar inductor with glass bonding shows excellent performance : inductance of 1.1 H, Q factor of 7 (at 5 MHz), and the dc current capability up to 100 mA.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• ETRI Journal
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• 제25권4호
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• pp.270-273
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• 2003

This paper presents a simple process to integrate thin-film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3${\mu}m$ were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin-film inductor showed an inductance of 0.49${\mu}H$ and a Q factor of 4.8 at 8 MHz. The DC-DC converter with the monolithically integrated thin-film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC-DC converter with the monolithic thin-film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.

• 전자공학회논문지D
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• 제34D권9호
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• pp.28-35
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• 1997

A novel high-Q vertical jinductor for MMICs is proposed and characterized in a wide range of frequencies (DC~10 GHz) using the numerical methods such as the PeEC(partial equivalent element circuit), the FDM (finite difference method) and the MoM (method of moments). Electrical superiority of the vertical inductor to the horizontal is observed in terms of the magnetic flux linkage and the ground screening effect. The veritcal bondwire inductor is designed in consideration of the wire bonding feasibility and the optimum electrical peformance. This structure is also analyzed using the equivalent circuit and compared with the conventional spiral inductors From the calculated results, high Q-factor, inductance, and cut-off frequency are observed to be inherent characteristics of the veritcal bondwire inductor.

• Journal of information and communication convergence engineering
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• 제4권4호
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• pp.155-157
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• 2006

This paper presents the thermal technique to improve characteristic of planar spiral inductors. The spiral inductors were fabricated on silicon dioxide/silicon (SiO2/Si) wafer. The thermal treatment was done by annealing processes. The measure results showed a considerable improvement of return loss (Sl1). This thermal treatment seems very promising for enhancing spiral inductors based RF IC's.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.890-893
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• 2004

In this study, Spiral inductors on the $SiO_2/Si$(100) substrate were fabricated by the magnetron sputtering method. Cu thin film with the thickness of 2 ${\mu}m$ was deposited on the substrate. Also we fabricated square inductors through the wet chemical etching technique. The inductors are completely specified by the turn width and the spacing between spirals. Both the width and spacing between spirals were varied from 10 to 60${\mu}m$ and from 20 to 70 ${\mu}m$, respectively. Inductance and Q factor dependent on the frequency were investigated to analyze performance of spiral inductors.