• Title/Summary/Keyword: Source Mismatch

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The Design of a Low Power and Wide Swing Charge Pump Circuit for Phase Locked Loop (넓은 출력 전압 범위를 갖는 위상동기루프를 위한 저전압 Charge Pump 회로 설계)

  • Pu, Young-Gun;Ko, Dong-Hyun;Kim, Sang-Woo;Park, Joon-Sung;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.44-47
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    • 2008
  • In this paper, a new circuit is proposed to minimize the charging and discharging current mismatch in charge pump for UWB PLL application. By adding a common-gate and a common-source amplifier and building the feedback voltage regulator, the high driving charge pump currents are accomplished. The proposed circuit has a wide operation voltage range, which ensures its good performance under the low power supply. The circuit has been implemented in an IBM 0.13um CMOS technology with 1.2V power supply. To evaluate the design effectiveness, some comparisons have been conducted against other circuits in the literature.

A Fabrication and Characteristics of GaInAs/InP PIN Phtodiode Grown by LPE (LPE에 의한 GaInAs/InP PIN Photodiode의 제작 및 특성)

  • 박찬용;남은수;박경현;김상배;박문수;이용탁;홍창희
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.5
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    • pp.737-746
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    • 1990
  • Ga0.47In0.53As PIN photodiodes(PD) having various areas have been fabricated by liquid phase epitaxial techniques. Ternary melt has been baked out at 675\ulcorner in H2 atmosphere for 20 hours before growth, which resulted in reduction of background carrier concentration of grown epi-layer. Also, lattice mismatch has been controlled within 0.01%. The room temperature performance of 10**-4cm\ulcornerarea PIN PD at a bias voltage of -5V were` quantum efficiency(with no antireflection coating)=60% for 1.3\ulcorner light source, dark current\ulcorner5nA, and capacitance\ulcornerpE. Frequency response measurement of packaged PIN PD has shown that cut-off frequency (f-3dB) was 961MHz. This PD has shown a good eye pattern when it was incorporated in a 565Mbps optical receiver.

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Touch Screen Sensing Circuit with Rotating Auto-Zeroing Offset Cancellation

  • Won, Dong-Min;Kim, HyungWon
    • Journal of information and communication convergence engineering
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    • v.13 no.3
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    • pp.189-196
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    • 2015
  • In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

Deposition and Photoluminescence Characteristics of Silicon Carbide Thin Films on Porous Silicon (다공성실리콘 위의 탄화규소 박막의 증착 및 발광특성)

  • 전희준;최두진;장수경;심은덕
    • Journal of the Korean Ceramic Society
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    • v.35 no.5
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    • pp.486-492
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    • 1998
  • Silicon carbide (SiC) thin films were deposited on the porous silicon substrates by chemical vapour de-position(CVD) using MTS as a source material. The deposited films were ${\beta}$-SiC with poor crystallity con-firmed by XRD measurement. It was considered that the films showed the mixed characteistics of cry-stalline and amorphous SiC where amorphous SiC where amorphous SiC played a role of buffer layer in interface between as-dep films and Si substrate. The buffer layer reduced lattice mismatch to some extent the generally occurs when SiC films are deposited on Si. The low temperature (10K) PL (phtoluminescence) studies showed two broad bands with peaks at 600 and 720 for the films deposited at 1100$^{\circ}C$ The maximum PL peak of the crystalline SiC was observed at 600 nm and the amrophous SiC of 720 nm was also confirmed. PL peak due the amorphous SiC was smaller than that of the crystalline SiC, PL of porous Si might be disapperared due to densification during heat treatment.

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Study on the Performance of Mismatched Quantizers on Weibull Sources (Weibull 신호원에 불일치 된 양자기 성능에 관한 연구)

  • 강신규;나상신
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2184-2187
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    • 2003
  • Quantizers for digital coding systems are usually optimized with respect to a model of the probability density function of the random variable to be quantized. Thus a mismatch of the quantizer relative to the actual statistics of the random variable may be unavoidable. This paper presents the results of an experimental investigation of mismatched quantizers. For the modeling of the source statistics, various types of the Weibull distribution are used, and the optimization of the quantizer is carried with respect to the minimum mean-square error (mse) criterion. The goal of this paper is to find an estimate formula for the mismatched quantizer on Weibull sources.

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Broadband CMOS Single-ended to Differential Converter for DVB-S2 Receiver Tuner IC (DVB-S2 수신기 튜너용 IC의 광대역 CMOS 단일신호-차동신호 변환기)

  • Shin, Hwa-Hyeong;Kim, Nam-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.185-185
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    • 2008
  • This paper describes the broadband SDC (Single-ended to Differential Converter) for Digital Video Broadcasting-Satellite $2^{nd}$ edition (DVB-S2) receiver tuner IC. It is fabricated by using $0.18{\mu}m$ CMOS process. In order to obtain high linearity and low phase mismatch, the broadband SDC (Single-ended to Differential Converter) is designed with current mirror structure and cross-coupled capacitor and current source binding differential structure at VDD. The simulation result of SDC shows IIP3 of 11.9 dBm and IIP2 of 38 dBm. It consumes 5mA current with 2.7V supply voltage.

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Investigation of charge injection in organic thin film transistor using ink-jet printed silver electrodes

  • Kim, Dong-Jo;Jeong, Sun-Ho;Lee, Sul;Jang, Dae-Hwan;Moon, Joo-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.730-732
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    • 2007
  • We fabricated a coplanar type organic thin-film transistors using ink-jet printed silver source/drain electrodes and ${\alpha},{\omega}-dihexylquaterthiophene$ (DH4T) which is an active layer. Use of ink-jet printed silver nanoparticle-based metal electrode assists the energetic mismatch with p-type organic semiconductor via modification of their interfacial properties to enable ohmic contact formation.

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System calibration method for Silicon wafer warpage measurement (실리콘 웨이퍼 휨형상 측정 정밀도 향상을 위한 시스템변수 보정법)

  • Kim, ByoungChang
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.13 no.6
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    • pp.139-144
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    • 2014
  • As a result of a mismatch of the residual stress between both sides of the silicon wafer, which warps and distorts during the patterning process. The accuracy of the warpage measurement is related to the calibration. A CCD camera was used for the calibration. Performing optimization of the error function constructed with phase values measured at each pixel on the CCD camera, the coordinates of each light source can be precisely determined. Measurement results after calibration was performed to determine the warpage of the silicon wafer demonstrate that the maximum discrepancy is $5.6{\mu}m$ with a standard deviation of $1.5{\mu}m$ in comparison with the test results obtained by using a Form TalySurf instrument.

Computation of Stress Field During Additive Manufacturing by Explicit Finite Element Method (외연적 유한요소법을 이용한 적층제조 공정 중 응력 장 변화 계산)

  • Yang, Seung-Yong;Kim, Jeoung Han
    • Journal of Powder Materials
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    • v.27 no.4
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    • pp.318-324
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    • 2020
  • In the present work, an explicit finite element analysis technique is introduced to analyze the thermal stress fields present in the additive manufacturing process. To this purpose, a finite element matrix formulation is derived from the equations of motion and continuity. The developed code, NET3D, is then applied to various sample problems including thermal stress development. The application of heat to an inclusion from an external source establishes an initial temperature from which heat flows to the surrounding body in the sample problems. The development of thermal stress due to the mismatch between the thermal strains is analyzed. As mass scaling can be used to shorten the computation time of explicit analysis, a mass scaling of 108 is employed here, which yields almost identical results to the quasi-static results.

An implementation of a magnetic-field measurement system based on optical sensor (광센서를 이용한 자기장 계측 장치 구현)

  • Kim, Young-Soo;Park, Byung-Seok;Kim, Myong-Soo;Lim, Yong-Hun;Hyun, Duck-Hwa
    • Proceedings of the KIEE Conference
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    • 2002.11a
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    • pp.219-222
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    • 2002
  • In this paper, some parameters are studied for the performance improvement of a bulk optical magnetic-field sensor. The performance of optical magnetic-field sensor is influenced by optical intensity change and wavelength change of light source, and phase shift so called optical bias mismatch. A magnetic field measuring system based on optical Faraday sensor is implemented and tested in the current range from 10 ampere to 200 ampere. The test result shows implemented system has goof linearity.

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