• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.485-489
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• 2015

An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.747-750
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• 2003

We have studied PHEMTs optimization by means of fabrication of PHEMTs. All PHEMTs have been fixed with a gate length of 0.1 ${\mu}{\textrm}{m}$, a gate head size of 0.75${\mu}{\textrm}{m}$, and two gate fingers. We have measured the characteristics of PHEMTs with variation of source-drain spacing, pad size, and gate width. As a result, we have found the enhanced characteristics of $I_{dss}$, $S_{21}$, $h_{21}$, $f_{T}$, $f_{max}$, and $G_{ms}$ with increasing gate width. Also, $g_{m}$ has improved with decreasing source-drain spacing, and $S_{21}$ has improved with deceasing pad size.e.e.e.e.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.37-47
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• 1997

Utilizing 2-dimensional device simulations incorporating lattic eheating models, we analyzed in detail the DC breakdown characterisics of NMOS trasistors with different structures, which are commonly used as ESD protection transistors. The mechanism leading to device failure resulting from electrostatic discharge was explained by analyzing the 1st and 2nd breakdown characteristics of LDD devices. Also a criteria for more robust designs of NMOS transistor structures against ESD was suggested by examining the characteristics changes with changes in structural parameters such as the LDD doping concentration, the drain junction depth, the distance between source/drain contacts, and the source junction area.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• ETRI Journal
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• v.20 no.2
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• pp.241-249
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• 1998

The structure and electrical characteristics of metal-ferroelectric-semiconductor FET(MFSFET) for a single transistor memory are presented. The MFSFET was comprised of polysilicon islands as source/drain electrodes and $BaMgF_4$ film as a gate dielectric. The polysilicon source and drain were built-up prior to the formation of the ferroelectric film to suppress a degradation of the film due to high thermal cycles. From the MFS capacitor, the remnant polarization and coercive field were measured to be about $0.6{\mu}C/cm^2$ and 100 kV/cm, respectively. The fabricated MFSFETs also showed good hysteretic I-V curves, while the current levels disperse probably due to film cracking or bad adhesion between the film and the Al electrode.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.443-443
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• 2012

We fabricated a-IGZO TFT with AZO/Ag/AZO transparent multilayer source/drain contacts by rf magnetron sputtering. Enhanced electrical device performance of a-IGZO TFT with AZO/Ag/AZO multilayer S/D electrodes (W/L = = 400/50 mm) was achieved with a subs-threshold swing of 3.78 V/dec, a minimum off-current of 10-12 A, a threshold voltage of 1.80 V, a field effect mobility of 10.86 cm2/Vs, and an on/off ration of 9x109. It demonstrated the potential application of the AZO/Ag/AZO film as a promising S/D contact material for the fabrication of the high performance TFTs.