• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.36-39
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• 2000

The adaptive learning circuit is designed the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportioned to the source-drain resistance of MFSFET and the capacitance of the circuit. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of imput pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristics of the adaptive learning circuit, that is, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.7
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• pp.433-438
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• 2015

Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated by using $n^+$ Si wafers as gate electrodes. Indium (In), aluminum (Al), indium tin oxide (ITO), silver (Ag), and gold (Au) were employed for source and drain electrodes, and the mobility and the threshold voltage of ZTO TTFTs were observed as a function of electrode. The ZTO TTFTs adopting In as electrodes showed the highest mobility and the lowest threshold voltage. It was shown that Ag and Au are not suitable for the electrodes of ZTO TTFTs. As the results of this study, it is considered that the interface properties of electrode/ZTO are more influential in the properties of ZTO TTFTs than the conductivity of electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• Journal of the Korean Society of Industry Convergence
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• v.10 no.4
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• pp.227-233
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• 2007

In case of design of a rectifier to supply high current, To select switching frequency of semiconductor switches affect absolutely the design of the LC filter value in an power conversion circuit. The conventional rectifier by using MOSFET is no use in high current equipments because of small drain-source current. To solve this problem, this paper proposes to design of high capacity rectifier by parallel driving of MOSFET in the single half bridge DC-DC converter. This method can be able to develop high current rectifier by distributed drain-source current. The proposed scheme is able to expect a decrease in size, weight and cost of production by decreasing the LC filter value and increasing maximumly the switching frequency. The validity of the proposed parallel driving strategy is verified through computer-aided simulations and experimental results.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1288-1291
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• 2007

We investigated the effect of Cr thickness on the electrical properties of triisopropylsilyl pentacene organic thin-film transistor (OTFT) employing suspended source-drain electrode. With Cr thickness of 10 nm, the field-effect mobility, on/off ratio and subthreshold slope were $0.017\;cm^2/Vs$, $8.78\;{\times}\;10^3$ and 10 V/decade, respectively. By increasing the Cr thickness to 100 nm, the fieldeffect mobility was increased to $0.032\;cm^2/Vs$, on/off ratio to $1.12{\times}10^5$ and subthreshold slope to 1 V/decade.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1312-1314
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• 2007

The effect of gate insulator surface treatment on electrical characteristics of bottom contact (BC) and suspended source/drain (SSD) organic thinfilm transistors (OTFTs) was studied. Triisopropylsilylethynyl pentacene was used as an active material and was printed by ink-jet printing method. In case of the BC OTFTs, threshold voltage was shifted from positive to near zero, and the fieldeffect mobility was increased when the gate insulator surface was treated with hexamethyldisilazane. However, in case of SSD OTFT, threshold voltage shift was not observed and the field-effect mobility was decreased.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.5
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• pp.48-53
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• 1998

Poly-Si TFT's could be fabricated on glass substrates by metal induced lateral crystallization (MILC) method at 450.deg. C. Channel area of the poly-Si TFT's was laterally crystallized from source and drain areas, where a thn nickel film was deposited. Dopants activation for the formation of source and drain region could be achieved by thermal annealing at 450.deg. C after the ion mass doping of phosphorus. The field effect mobility of thus formed N-channel poly-Si TFT's was 76cm$^{2}$/Vs, and the on/off current ratio was higher than 7E6.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.635-640
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• 2016

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.254-257
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• 2008

We have investigated the effect of source/drain electrode deposition method on a performance of top gate structured ZnO TFT performance. TFT using S/D of ITO film, consisted of bi-layer which deposited by ion beam assisted sputtering at the initial stage then deposited by DC magnetron sputtering, showed better performance compared to that using S/D of ITO deposited by just DC magnetron sputtering. Two ITO films exhibited different grain shapes and these resulted in different etching properties. We also suspect that charge trapping on the glass substrate (back channel) during the ITO film deposition may influence the characteristics of top gate structured ZnO TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.597-600
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• 2006

The silver gate and source/drain electrodes for an a-Si thin film transistor were fabricated by the selective electroless plating (SELP) process. Relevant physical properties including taper angle, uniformity and resistivity are investigated. The Ag layer was about 150nm to 250nm thick, the resistivity less than $3{\times}10^{-6}$ Ohm-cm and the taper angle 45'-60' and the nonuniformity less than 10% on G2 substrates. The transfer characteristics with the Ag gate, and source/drain electrodes respectively possessed good field effect mobility similar to conventionally fabricated a-Si TFTs. This process provided low resistivity, low cost and ease of processing.