• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.1-9
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• 2011

Understanding the void characterization in the solder joints has become more important because of the application of lead free solder materials and its reliability in electronic packaging technology. According to the JEDEC 217 standard, it describes void types formed in the solder joints, and divides into some categories depending on the void position and formation cause. Based on the previous papers and the standards related to the void, reliability of the BGA solder joints is determined by the size of void, as well as the location of void inside the BGA solder ball. Prior to reflow soldering process, OSP(organic surface preservative) finished Cu electrode was exposed under $85^{\circ}C$/60%RH(relative humidity) for 168 h. Voids induced by the exposure of $85^{\circ}C$/60%RH became larger and bigger with increasing aging times. The void position has more influence on mechanical strength property than the amount of void growth does.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.33-37
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• 2008

A noticeable amount of Kirkendall voids formed at the Sn-3.5Ag solder joint with electroplated Cu, and that became even more significant when an additive was added to Cu electroplating bath. With SPS, a large amount of voids formed at the $Cu/Cu_3Sn$ interface of the solder joint during thermal aging at $150^{\circ}C$. The in-situ AES analysis of fractured joints revealed S segregation on the void surface. Only Cu, Sn, and S peaks were detected at the fractured $Cu/Cu_3Sn$ interfaces, and the S peak decreased rapidly with AES depth profiling. The segregation of S at the $Cu/Cu_3Sn$ interface lowered interface energy and thereby reduced the free energy barrier for the Kirkendall void nucleation. The drop impact test revealed that the electrodeposited Cu film with SPS degraded drastically with aging time. Fracture occurred at the $Cu/Cu_3Sn$ interface where a lot of voids existed. Therefore, voids occupied at the $Cu/Cu_3Sn$ interface are shown to seriously degrade drop reliability of solder joints.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.49-54
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• 1993

This paper discusses the reliability of solder joints of electronic devices on printed circuit board. Solder application is usually done by screen printing method for the bonding between outer leads of devices and thick film(Ag/Pd) pattern on Hybrid IC as wel1 as Cu lands on PCB. As result of thermal stresses generated at the solder joints due to the differences of thermal expansion coefficients between packge body and PCB, Micro cracking often occurs due to thermal fatigue failure at solder joints. The initiation and the propagate of solder joint crack depends on the environmental conditions, such as storage temperature and thermal cycling. The principal mechanisms of the cracking pheno- mana are the formation of kirkendal void caused by the differences in diffusion rate of materials, ant the thermal fatigue effect due to the differences of thermal expansion coefficient between package body and PCB. Finally, This paper experimentally shows a way to supress solder joints cracks by using low-${\alpha}$ PCB and the packages with thin lead frame, and investigates the phenomena of diffusion near the bonding interfaces.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.126-130
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• 2021

The ball grid array is one of the packaging methods that used in high density printed circuit board. Solder void defects caused by voids in the solder ball during the BGA process do not directly affect the reliability of the product, but it may accelerate the aging of the device on the PCB layer or interface surface depending on its size or location. Void inspection is important because it is related in yields with products. The most important process in the optical inspection of solder void is the segmentation process of solder and void. However, there are several segmentation algorithms for the vision inspection, it is impossible to inspect all of images ideally. When X-Ray images with poor contrast and high level of noise become difficult to perform image processing for vision inspection in terms of software programming. This paper suggests the solution to deal with the suggested problem by means of using Mask R-CNN instead of digital image processing algorithm. Mask R-CNN model can be trained with images pre-processed to increase contrast or alleviate noises. With this process, it provides more efficient system about complex object segmentation than conventional system.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.5
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• pp.151-156
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• 2007

In this paper, the creep characteristics of lead and lead-free solder joint were investigated using the QFP(Quad Flat Package) creep test. Two kind of solder pastes(Sn-3Ag-0.5Cu, Sn-0.2Sb-0.4Ag-37.4Pb) were applied to the QFP solder joints and each specimen was checked the external and internal failures(i.e., wetting failure, void, pin hole, poor-heel fillet) by digital microscope and X-ray inspection. The creep test was conducted at the temperatures of $100^{\circ}C$ and $130^{\circ}C$ under the load of 15$\sim$20% of average pull strength in solder joints. The creep characteristics of each solder joints were compared using the creep strain-time curve and creep strain rate-stress curves. Through the comparison, the Sn-3Ag-0.5Cu solder joints have higher creep resistance than that of Sn-0.3Sb-0.4Ag-37.4Pb. Also, the grain boundary sliding in the fracture surface and the necking of solder joint were observed by FE-SEM.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.1-26
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• 2004

The implementation of Pb-free solder technology is making good progress in electronic industry. Further understanding on fundamental issues on Pb-free solders/processes is required to reduce reliability risk factors of Pb-free solder joints. Several reliability issues including thermal fatigue, impact reliability, IMC growth, spalling, void formation are reviewed for Pb-free solder joints. Several applications of Pb-free technology are discussed, such as Pb-free, CBGA, CuCGA, flip chips, and wafer bumping by IMS.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.23-27
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• 2017

This paper proposes an approach to predict the reliability of high temperature heaters by identifying their primary failure modes and mechanisms in the field. Test specimens were designed to have the equivalent stress conditions with the high temperature heaters in the field in order to examine the effect of stress conditions on the solder joint failures. There failures often result from cracking due to intermetallic compound (IMC) or void formation within a solder joint. Aging tests have been performed by exposing the test specimens to a temperature of $170^{\circ}C$ in order to reproduce solder joint failures in the field. During the test, changes in IMC formation were investigated by scanning electron microscopy (SEM) on the cross-sections of the test specimens, while changes in void formation were monitored both by resistance spectroscopy and by micro-computed tomography (microCT), alternately. The test results demonstrated the void volume within the solder increased as the time at the high temperature increased. Also, the phase shift of high frequency resistance was found to have high correlation with the void volume. These results implied the failure of high temperature heaters can be non-destructively predicted based on the correlation.

• Advances in materials Research
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• v.1 no.1
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• pp.83-92
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• 2012

The effect of under-bump-metallization (UBM) on electromigration was investigated at temperatures ranging from $135^{\circ}C$ to $165^{\circ}C$. The UBM structures were examined: 5-${\mu}m$-Cu/3-${\mu}m$-Ni and $5{\mu}m$ Cu. Experimental results show that the solder joint with the Cu/Ni UBM has a longer electromigration lifetime than the solder joint with the Cu UBM. Three important parameters were analyzed to explain the difference in failure time, including maximum current density, hot-spot temperature, and electromigration activation energy. The simulation and experimental results illustrate that the addition 3-${\mu}m$-Ni layer is able to reduce the maximum current density and hot-spot temperature in solder, resulting in a longer electromigration lifetime. In addition, the Ni layer changes the electromigration failure mode. With the $5{\mu}m$ Cu UBM, dissolution of Cu layer and formation of $Cu_6Sn_5$ intermetallic compounds are responsible for the electromigration failure in the joint. Yet, the failure mode changes to void formation in the interface of $Ni_3Sn_4$ and the solder for the joint with the Cu/Ni UBM. The measured activation energy is 0.85 eV and 1.06 eV for the joint with the Cu/Ni and the Cu UBM, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.1
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• pp.35-42
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• 2024

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.