• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.95-103
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• 2005

The interfacial reaction between 42Sn-58Bi solder (in wt.$\%$ unless specified otherwise) and electroless Ni-P/immersion Au has been investigated before and after thermal aging, with a focus on formation and growth of an intermetallic compound (IMC) layer, consumption of under bump metallurgy (UBM), and bump shear strength. The immersion Au layer with thicknesses of 0 (bare Ni), 0.1, and $1{\mu}m$ was plated on the $5{\mu}m$ thick electroless Ni-P ($14{\~}15 at.\%$P) layer. Then, the 42Sn-58Bi solder balls were fabricated on three different UBM structures by screen-printing and pre-reflow. The $Ni_3Sn_4$ layer (IMC1) was formed at the joint interface after pre-reflow for all the three UBM structures. On aging at $125^{\circ}C$, a quaternary phase (IMC2) was observed above the $Ni_3Sn_4$ layer in the Au-containing UBM structures, which was identified as $Sn_{77}Ni{15}Bi_6Au_2$ (in at.$\%$). The thick $Sn_{77}Ni{15}Bi_6Au_2$ layer deteriorated the integrity of the solder joint and the shear strength of the solder bump was decreased by about $40\%$ compared with non-aged joints.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.77-82
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• 2012

In this paper, the research of IC embedded PCB process is carried out. For embedding chips into PCB, solder-balls on chips were etched out and ABF(Ajinomoto Build-ip Film), prepreg and Cu foil was laminated on that to fabricate 6 layer build-up board. The chip of which solder ball was removed was successfully interconnected with PCB by laser drilling and Cu plating. However, de-lamination phenomenon occurred between chip surface and ABF during reflow and thermal shock. To solve this problem, de-smear and plasma treatment was applied to PI(polyimide) passivation layer on chip surface to improve the surface roughness. The properties of chip surface(PI) was investigated in terms of AFM(Atomic Force Micrometer), SEM and XPS (X-ray Photoelectron Spectroscopy). As results, nano-size anchor was evenly formed on PI surface when plasma treatment was combined with de-smear(NaOH+KMnO4) process and it improved thermal shock reliability ($260^{\circ}C$-10sec solder floating).

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.1
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• pp.45-50
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• 2014

A vibration test coupon is prepared with nine plastic ball grid array packages on a printed circuit board using SnPb solders, and a random vibration test is conducted on the coupon. Life data from the test are analyzed, and it is shown that over the board, life data is location-dependent. For investigating this location dependency, a finite element model is developed and the equivalent stresses, which are defined based on the stress response functions at each node, are investigated. It is shown that one of the corner solder balls has the maximum equivalent stress at a package during the test. Finally, it is demonstrated that the maximum equivalent stress and durability life are inversely proportional.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.17-25
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• 2006

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $moir\'{e}$ interferometry. $Moir\'{e}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for both single and double-sided package assemblies are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one because of its symmetric structure. The largest effective strain occurred at the solder ball located on the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one by 50%.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.80-83
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• 2003

본 연구에서는 고온 솔더 범프와 저온 솔더 패드를 이용하여 $140^{\circ}C$에서 1분간의 리플로 공정을 통해 접합에 성공하였다. 고온 솔더 범프로 Sn-4.0Ag-0.5Cu 솔더 볼을 사용하였고, 저온 솔더는 In-48Sn $(mp:\;117^{\circ}C)$ 솔더를 기판에 evaporation 방법으로 두께 $20\;{\mu}m$의 패드 형태로 증착하였다. $140^{\circ}C$에서 1분간의 리플로 공정을 통해 칩과 기판을 접합하였으며, 접합 단면을 관찰해 본 결과 저온 솔더가 녹아 고온 솔더에 wetting된 것을 관찰하였다. 이 시편을 상온에서 시효처리를 실시한 결과 시간의 경과에 따라 저온 솔더와 고온 솔더가 상호 확산하여 약 $40\;{\mu}m$였던 확산층의 범위가 점차 증가하는 것을 관찰할 수 있었다. 또한, 리플로 공정변수에 따른 솔더의 미세구조 변화 및 ball shear strength등의 기계적 특성에 대해 고찰하였다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.11
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• pp.1646-1655
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• 2004

A description of the basic principles of moire interferometry leads to the design of a eight-mirror four-beam interferometer for obtaining fringe patterns representing contour-maps of in-Plane displacements. The technique is implemented by the optical system using an environmental chamber for submicro-displacement mesurement. In order to estimate the reliability and applicabili쇼 of the system developed, the measurement of coefficient of thermal expansion (CTE) for a aluminium block is performed. Consequently, the system is applied to the measurement of thermal deformation of a WB-PBGA package assembly. Temperature dependent analyses of global and local deformations are presented to study the effect of the mismatch of CTE between materials composed of the package assemblies. Bending displacements of the packages and average strains of solder balls are documented. Thermal induced displacements calculated by FEM agree quantitatively with experimental results.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.98-103
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• 2002

BGA(Ball Grid Array) 패키지의 솔더볼 패드 중의 하나인 Au/Ni-Co/Cu 금속층 위에 Bi가 첨가된 Sn-3.5Ag-$\chi$Bi 솔더볼을 리플로우시켰다. 리플로우한 후 130 $^{\circ}C$에서 열처리함에 따른 계면상 및 솔더 내부의 상변화를 관찰하였다. 계면에는 (Ni,Co)$_3$Sn$_4$외에 (Au,Ni,Co,Bi)Sn$_4$가 생성되었음을 관찰할 수 있었고, 솔더 내부에는 (Au,Ni,Co,Bi)SH$_4$, Ag$_3$Sn, Bi 상이 혼재되어 있었다. Nano-indentation에 의한 경도 측정 결과, Bi 함량 증가에 따라 경도는 증가하였으나, 볼전단(Ball Shear) 테스트 결과는 Bi가 증가됨에 따라 오히려 볼전단 강도값이 감소하였다. 이는 파면 검사 결과, 파괴 경로가 주로 계면의 금속간 화합물과 솔더 사이에서 진행함에 기인한 것이다. 솔더 내부의 파괴 경로를 가진 2.5Bi가 가장 우수한 볼전단 강도값을 나타내었는데, 이는 솔더내의 Bi의 고용강화에 기인한 것으로 보인다.

• Korean Journal of Materials Research
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• v.9 no.3
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• pp.288-294
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• 1999

In the flip chip interconnection using solder bump, the Under Bump Metallurgy (UBM) is required to perform multiple functions in its conversion of an aluminum bond pad to a solderable surface. In this study, various UBM systems such as $Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 5\mu\textrm{m}, Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}, al 1\mu\textrm{m}/Ni 0.2\mu\textrm{m} / Cu 1\mu\textrm{m} and Al 1\mu\textrm{m}/Pd 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}$ for flip chip interconnection using the low melting point eutectic 63Sn-37Pb solder were investigated and compared to their metallurgical properties. $100\mu\textrm{m}$ size bumps were prepared for using an electroplating process. The effects of the number of reflows and aging time on the growth of intermetallic compounds(IMC) were investigated. $Cu_6Sn_5$ and $Cu_3Sn$ IMC were abserved after aging treatment in the UBM system with thick coper $(Al 1\mu\textrm{m}/Ti 0.2\mu\textrm{m}/Cu 5\mu\textrm{m})$. However only the $Cu_6Sn_5$ was detected in the UBM system with $1\mu\textrm{m}$ thick copper even after 2 reflow and 7 day aging at $150^{\circ}C$. Complete Cu consumption by Cu-Sn IMC growth gives rise to a direct contact between solder inner layer such as Ti, Ni and Pd, and hence to possibly cause reactions between two of them. In this study, however, only for the Pd case, IMC of PdSn. was observed by Cu consumption. UBM interfacial reactions with s이der affected the adhesion strength ot s이der balls after s이der reflow and annealing treatment.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.