• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.322-322
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• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.

• Journal of the Korean Institute of Gas
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• v.26 no.5
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• pp.35-40
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• 2022

PCVD (Plasma Chemical Vapor Deposition), a solar cell manufacturing facility, is a facility that deposits plasma generated in a chamber (NH₃, SIH₄, O₂ on a wafer. In the PCVD facility, gas movement and injection is performed in the gas cabinet, and there are many leak points inside because MFC, regulator, valve, pipe, etc. are intricately connected. In order to prevent explosion in case of leakage of NH₃ with an upper explosive limit (UEL) of 33.6% and a lower explosive limit (LEL) of 15%, the dilution capacity must be capable of allowing the concentration of NH₃ to be out of the explosive range. This study was analyzed using the CFD analysis technique, which can confirm the dilution ability in 3D and numerical values when NH₃ gas leaks from the existing PCVD gas cabinet. As a result, it was concluded that it corresponds to medium dilution and that testicular ventilation is possible through facility improvement.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.204-205
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• 2011

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is a most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. For best performance of thin film silicon solar cell, the dopant profiles at p/i and i/n interfaces need to be as sharp as possible. The sharpness of dopant profiles can easily achieved when using multi-chamber PECVD equipment, in which each layer is deposited in separate chamber. However, in a single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of a single-chamber PECVD system in spite of the advantage of lower initial investment cost for the equipment. In order to resolve the cross-contamination problem in single-chamber PECVD systems, flushing method of the chamber with NH3 gas or water vapor after doped layer deposition process has been used. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. A single-chamber VHF-PECVD system was used for superstrate type p-i-n a-Si:H solar cell manufacturing on Asahi-type U FTO glass. A 80 MHz and 20 watts of pulsed RF power was applied to the parallel plate RF cathode at the frequency of 10 kHz and 80% duty ratio. A mixture gas of Ar, H2 and SiH4 was used for i-layer deposition and the deposition pressure was 0.4 Torr. For p and n layer deposition, B2H6 and PH3 was used as doping gas, respectively. The deposition temperature was $250^{\circ}C$ and the total p-i-n layer thickness was about $3500{\AA}$. In order to remove the deposited B inside of the vacuum chamber during p-layer deposition, a high pulsed RF power of about 80 W was applied right after p-layer deposition without SiH4 gas, which is followed by i-layer and n-layer deposition. Finally, Ag was deposited as top electrode. The best initial solar cell efficiency of 9.5 % for test cell area of 0.2 $cm^2$ could be achieved by applying the in-situ plasma cleaning method. The dependence on RF power and treatment time was investigated along with the SIMS analysis of the p-i interface for boron profiles.

• Journal of Institute of Convergence Technology
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• v.8 no.1
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• pp.33-39
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• 2018

The screen printing method for forming the electrode by applying the existing pressure is difficult to apply to thin wafers, and since expensive Ag paste is used, it is difficult to solve the problem of cost reduction. This can solve both of the problems by forming the front electrode using a plating method applicable to a thin wafer. In this paper, the process conditions of electrode formation are optimized by using LIEP (Light-Induced Electrode Plating). Experiments were conducted by varying the Ni plating bath temperature $40{\sim}70^{\circ}C$, the applied current 5 ~ 15 mA, and the plating process time 5 ~ 20 min. As a result of the experiment, it was confirmed that the optimal condition of the structural characteristics was obtained at the plating bath temperature of $60^{\circ}C$, 15 mA, and the process time of 20 min. The Cu LIEP process conditions, experiments were conducted with Cu plating bath temperature $40{\sim}70^{\circ}C$, applied voltage 5 ~ 15 V, plating process time 2 ~ 15 min. As a result of the experiment, it was confirmed that the optimum conditions were obtained as a result of electrical and structural characteristics at the plating bath temperature of $60^{\circ}C$ and applied current of 15 V and process time of 15 min. In order to form Ni silicide, the firing process time was fixed to 2 min and the temperature was changed to $310^{\circ}C$, $330^{\circ}C$, $350^{\circ}C$, and post contact annealing was performed. As a result, the lowest contact resistance value of $2.76{\Omega}$ was obtained at the firing temperature of $310^{\circ}C$. The contact resistivity of $1.07m{\Omega}cm^2$ can be calculated from the conditionally optimized sample. With the plating method using Ni / Cu, the efficiency of the solar cell can be expected to increase due to the increase of the electric conductivity and the decrease of the resistance component in the production of the solar cell, and the application to the thin wafer can be expected.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.3
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• pp.139-143
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• 2017

N-type crystalline silicon solar cells have high metal impurity tolerance and higher minority carrier lifetime that increases conversion efficiency. However, junction quality between the boron diffused layer and the n-type substrate is more important for increased efficiency. In this paper, the current status and prospects for boron diffused layers in N-type crystalline silicon solar cell applications are described. Boron diffused layer formation methods (thermal diffusion and co-diffusion using $a-SiO_X:B$), boron rich layer (BRL) and boron silicate glass (BSG) reactions, and analysis of the effects to improve junction characteristics are discussed. In-situ oxidation is performed to remove the boron rich layer. The oxidation process after diffusion shows a lower B-O peak than before the Oxidation process was changed into $SiO_2$ phase by FTIR and BRL. The $a-SiO_X:B$ layer is deposited by PECVD using $SiH_4$, $B_2H_6$, $H_2$, $CO_2$ gases in N-type wafer and annealed by thermal tube furnace for performing the P+ layer. MCLT (minority carrier lifetime) is improved by increasing $SiH_4$ and $B_2H_6$. When $a-SiO_X:B$ is removed, the Si-O peak decreases and the B-H peak declines a little, but MCLT is improved by hydrogen passivated inactive boron atoms. In this paper, we focused on the boron emitter for N-type crystalline solar cells.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.9
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• pp.823-828
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• 2013

To reduce the cost per watt of photovoltaic power, it is important to reduce the cell thickness of crystalline silicon solar cells. As the thickness of the silicon layer is reduced, two distinctive thermal expansion rates between the silicon and the aluminum layer induce bowing in a solar cell. With a thinner silicon layer, the bowing distance grows exponentially. Excessive bowing could damage the silicon wafer. In this study, we tried to measure an irregularly curved silicon solar cell more accurately using a 3D image scanner. For the detailed analysis of the three-dimensional bowing shape, a least square fit was applied to the point data from the scanned image. It has been found that the bowing distance and shape distortion increase with a decrease in the thickness of the silicon layer. An Ag strip on top of the silicon layer can reduce the bowing distance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.240-244
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• 2011

The high cost of crystalline silicon solar cells has been considered as one of the major obstacles to their terrestrial applications. Spin on doping (SOD) is presented as a useful process for the manufacturing of low cost solar cells. Phosphorus (P509) was used as an n-type emitters of solar cells. N-type emitters were formed on p-type EFG ribbon Si wafers by using a SOD at different spin speed (1,000~4,000 rpm), diffusion temperatures ($800^{\circ}C{\sim}950^{\circ}C$), and diffusion time (5~30 min) in $N_2+O_2$ atmosphere. With optimum condition, we were able to achieve cell efficiency of 14.1%.

• Korean Journal of Materials Research
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• v.29 no.5
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• pp.322-327
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• 2019

Hole carrier selective MoOx film is obtained by atomic layer deposition(ALD) using molybdenum hexacarbonyl[$Mo(CO)_6$] as precursor and ozone($O_3$) oxidant. The growth rate is about 0.036 nm/cycle at 200 g/Nm of ozone concentration and the thickness of interfacial oxide is about 2 nm. The measured band gap and work function of the MoOx film grown by ALD are 3.25 eV and 8 eV, respectively. X-ray photoelectron spectroscopy(XPS) result shows that the $Mo^{6+}$ state is dominant in the MoOx thin film. In the case of ALD-MoOx grown on Si wafer, the ozone concentration does not affect the passivation performance in the as-deposited state. But, the implied open-circuit voltage increases from $576^{\circ}C$ to $620^{\circ}C$ at 250 g/Nm after post-deposition annealing at $350^{\circ}C$ in a forming gas ambient. Instead of using a p-type amorphous silicon layer, high work function MoOx films as hole selective contact are applied for heterojunction silicon solar cells and the best efficiency yet recorded (21 %) is obtained.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.1-9
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• 2013

Recently flexible electronic devices have attracted a great deal of attention because of new application possibilities including flexible display, flexible memory, flexible solar cell and flexible sensor. In particular, development of flexible memory is essential to complete the flexible integrated systems such as flexible smart phone and wearable computer. Research of flexible memory has primarily focused on organic-based materials. However, organic flexible memory has still several disadvantages, including lower electrical performance and long-term reliability. Therefore, emerging research in flexible electronics seeks to develop flexible and stretchable technologies that offer the high performance of conventional wafer-based devices as well as superior flexibility. Development of flexible memory with inorganic silicon materials is based on the design principle that any material, in sufficiently thin form, is flexible and bendable since the bending strain is directly proportional to thickness. This article reviews progress in recent technologies for flexible memory and flexible electronics with inorganic silicon materials, including transfer printing technology, wavy or serpentine interconnection structure for reducing strain, and wafer thinning technology.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.214-217
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• 2006

p-type 비정질 실리콘 에미터와 n-type 실리콘 기판의 계면에 intrinsic 비정질 실리콘을 증착함으로써 계면의 재결합을 억제하여 20%가 넘는 효율을 보이는 이종접합 태양전지가 Sanyo에 의해 처음 제시된 후 intrinsic layer에 대한 연구가 많이 진행되어 왔다. 하지만 p-type wafer의 경우는 n-type에 비해 intrinsic buffer의 효과가 미미하거나 오히려 특성을 저하시킨다는 보고가 있으며 그 이유로는 minority carrier에 대한 barrier가 상대적으로 낮다는 것과 partial epitaxy가 발생하기 때문으로 알려져 있다. 본 연구에서는 partial epitaxy를 억제하기 위한 방법으로 증착 온도를 낮추고 QSSPC를 사용하여 minority carrier lifetime을 측정함으로써 각 온도에 따른 passivation 특성을 평가하였다. 또한 SiH4에 H2를 섞어서 증착하였을 경우 각 dilution ratio(H2 flow/SiH4 flow)에서의 passivation 특성 또한 평가하였다. 기판 온도 $100^{\circ}C$에서 증착된 샘플의 lifetime이 가장 길었으며 그 이하와 이상에서는 lifetime이 감소하는 경향을 보였다 낮은 온도에서는 박막 자체의 결함이 증가하였기 때문이며 높은 온도에서는 partial epitaxy의 영향으로 추정된다. H2 dilution을 하여 증착한 샘플의 경우 SiH4만 가지고 증착한 샘플보다 훨씬 높은 lifetime을 가졌다 이 또한 박막 FT-IR결과로부터 H2 dilution을 한 경우 compact한 박막이 형성되는 것을 확인할 수 있었는데 radical mobility 증가에 의한 박막 특성 향상이 원인으로 생각된다.