• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.364-367
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• 2012

In this paper, AXI4 BUS was implemented using Verilator and C/C++ for verification of SoC platform H/W IP which is based on AXI4 BUS. In this paper we proposed a method to verify the AXI4 BUS based SoC platform H / W IP by implemented AXI4 BUS on PC using Verilator and C/C++. The result shows AXI4 BUS based H/W IP that is verified by implemented AXI4 BUS is to perform the same behavior on FPGA environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1653-1658
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. In this study, we compare the characteristics of various arbitration policies using TLM(Transaction Level Model) method. Fixed priority, round-robin, TDMA and Lottery bus policies are used in general arbitration method. We analyze the merit and demerit of these arbitration policies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.50-56
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.