• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.110.1-110.1
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• 2012

Recently, advances in ZnO based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). However, the electrical performances of oxide semiconductors are significantly affected by interactions with the ambient atmosphere. Jeong et al. reported that the channel of the IGZO-TFT is very sensitive to water vapor adsorption. Thus, water vapor passivation layers are necessary for long-term current stability in the operation of the oxide-based TFTs. In the present work, $Al_2O_3$ and $TiO_2$ thin films were deposited on poly ether sulfon (PES) and $SnO_x$-based TFTs by electron cyclotron resonance atomic layer deposition (ECR-ALD). And enhancing the WVTR (water vapor transmission rate) characteristics, barrier layer structure was modified to $Al_2O_3/TiO_2$ layered structure. For example, $Al_2O_3$, $TiO_2$ single layer, $Al_2O_3/TiO_2$ double layer and $Al_2O_3/TiO_2/Al_2O_3/TiO_2$ multilayer were studied for enhancement of water vapor barrier properties. After thin film water vapor barrier deposited on PES substrate and $SnO_x$-based TFT, thin film permeation characteristics were three orders of magnitude smaller than that without water vapor barrier layer of PES substrate, stability of $SnO_x$-based TFT devices were significantly improved. Therefore, the results indicate that $Al_2O_3/TiO_2$ water vapor barrier layers are highly proper for use as a passivation layer in $SnO_x$-based TFT devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.543-543
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• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.127-127
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• 2011

We investigate the transparent TFTs using a transparent ZnSnO3 (ZTO)/Ag/ZTO multilayer electrode as S/D electrodes with low resistivity of $3.24{\times}10^{-5}$ ohm-cm, and high transparency of 86.29% in ZTO based TFTs. The Transparent TFTs (TTFTs) are prepared on glass substrate coated 100 nm of ITO thin film. On atomic layer deposited $Al_2\;O_3$, 50 nm ZTO layer is deposited by RF magnetron sputtering through a shadow mask for channel layer using ZTO target with 1 : 1 molar ratio of ZnO : $SnO_2$. The power of 100W, the working pressure of 2mTorr, and the gas flow of Ar 20 sccm during the ZTO deposition. After channel layer deposition, a ZTO (35 nm)/Ag (12 nm)/ZTO(35 nm) multilayer is deposited by DC/RF magnetron sputtering to form transparent S/D electrodes which are patterned through the shadow mask. Devices are annealed in air at 300$^{\circ}C$ for 30 min following ZTO deposition. Using UV/Visible spectrometer, the optical transmittances of the TTFT using ZTO/Ag/ ZTO multilayer electrodes are compared with TFT using Mo electrode. The structural properties of ZTO based TTFT with ZTO/Ag/ZTO multilayer electrodes are analyzed by high resolution transmission electron microscopy (HREM) and X-ray photoelectron spectroscopy (XPS). The transfer and output characterization of ZTO TTFTs are examined by a customized probe station with HP4145B system in are.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.166-166
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• 2010

Recently, TFTs based on amorphous oxide semiconductors (AOSs) such as ZnO, InZnO, ZnSnO, GaZnO, TiOx, InGaZnO(IGZO), SnGaZnO, etc. have been attracting a grate deal of attention as potential alternatives to existing TFT technology to meet emerging technological demands where Si-based or organic electronics cannot provide a solution. Since, in 2003, Masuda et al. and Nomura et al. have reported on transparent TFTs using ZnO and IGZO as active layers, respectively, much efforts have been devoted to develop oxide TFTs using aforementioned amorphous oxide semiconductors as their active layers. In this thesis, I report on the performance of thin-film transistors using amorphous indium gallium zinc oxides for an active channel layer at room temperature. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium gallium zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium gallium zinc oxide was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 1.5V and an on/off ration of > $10^9$ operated as an n-type enhancement mode with saturation mobility with $9.06\;cm^2/V{\cdot}s$. The devices show optical transmittance above 80% in the visible range. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium gallium zinc oxides for an active channel layer were reported. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.