• Title/Summary/Keyword: Small-signal

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New developmental direction of telecommunications for Disabilities Welfare (장애인복지를 위한 정보통신의 발전방향)

  • 박민수
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.1
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    • pp.35-43
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    • 2000
  • This paper was studied on developmental direction of telecommunications for disabilities welfare. Method of this study is delphi method. Persons with disabilities is classed as motor disability, visual handicap, hearing impairment, and language and speech disorders. Persons with motor disability is needs as follow, speed recognition technology, video recognition technology, breath capacity recognition technology. Persons with visual handicap is needs as follow, display recognition technology, speed recognition technology, text recognition technology, intelligence conversion handling technology, video recognition - speed synthetic technology. Persons with hearing impairment and language - speech disorders is needs as follow, speed signal handling technology, speed recognition technology, intelligence conversion handling technology, video recognition technology, speed synthetic technology the results of this study is as follow: first, disabilities telecommunications organization must be constructed. Second, persons with disabilities in need of universal service. Third, Persons with disabilities in need of information education, Fourth, studying for telecommunications in need of support. Fifth, small telecommunications company in need of support. Sixth, software industry in need of new development. Seventh, Persons with disabilities in need of standard guideline for telecommunications.

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A Design of Low-power/Small-area Divider and Square-Root Circuits based on Logarithm Number System (로그수체계 기반의 저전력/저면적 제산기 및 제곱근기 회로 설계)

  • Kim, Chay-Hyeun;Kim, Jong-Hwan;Lee, Yong-Hwan;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.895-898
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    • 2005
  • This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

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Analysis of Pseudolite Augmentation for Vessel Berthing

  • Cho, Deuk-Jae;Park, Sang-Hyun;Suh, Sang-Hyun
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.1
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    • pp.15-19
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    • 2006
  • GPS has been increasingly exploited to provide positioning and navigation solutions for a variety of applications. In vessel berthing application, however, there are stringent requirements in terms of positioning accuracy, availability and integrity that cannot be satisfied by GPS alone. This is because the performance of satellite-based positioning and navigation systems are heavily dependent on both the number and the geometric distribution of satellite tracked by receivers. Due to the limited number of GPS satellites, a sufficient number of ‘visible’ satellites cannot be sometimes guaranteed. This paper discusses some issues associated with the implementation of ground-based pseudolite augmentation for vessel berthing. Pseudolite means small transmitter that transmits GPS-like signals in local area. Actually, pseudolite can play three different roles in GPS augmentation scheme, depending on the operational conditions. Firstly, in the case of kinematic GPS operation where there are no signal blockages, and more than five satellites are available, additional pseudolites strengthen the GPS satellite-pseudolite geometry, and more accurate and reliable positioning solution can be achieved. Secondly, in the case when there are adverse GPS operational environments in which the number of tracked satellites is less than four, pseudolites can complement the GPS signals. In the third case, GPS signals are completely unavailable, such as when operated indoor. In such cases the pseudolites can replace the satellite constellation. However, the first role will be considered in this paper, since more than four satellite signals can usually be tracked in most marine applications. This paper presents that the pseudolite-augmented precise positioning system can provides continuous centimeter-level positioning accuracy through comparison analysis of RDOP simulation result of the GPS satellite constellation and the pseudolite-augmented GPS satellite constellation.

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A Design of Viterbi Decoder by State Transition Double Detection Method for Mobile Communication (상태천이 이중검색방식의 이동통신용 Viterbi 디코더 설계)

  • 김용노;이상곤;정은택;류흥균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.4
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    • pp.712-720
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    • 1994
  • In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.

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Sintering and Microwave Dielectric Properties of $ZnWO_4$ ($ZnWO_4$ 소결특성 및 고주파 유전특성)

  • 이경호;김용철
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11a
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    • pp.386-389
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    • 2001
  • In this study, development of a new LTCC material using non-glassy system was attempted with respect to reducing the fabrication process steps and cost down. Lowering the sintering temperature can be achieved by liquid phase sintering. However, presence of liquid phases usually decrease dielectric properties, especially the quality factor. Therefore, the starting material must have quality factor as high as possible in microwave frequency range. And also, the material should have a low dielectric constant for enhancing the signal propagation speed. Regarding these factors, dielectric constants of various materials were estimated by the Clausius-Mosotti equation. Among them, ZnWO$_4$ was turned out the suitable LTCC material. ZnWO$_4$ can be sintered up to 98% of full density at 105$0^{\circ}C$ for 3 hours. It's measured dielectric constant, quality factor, and temperature coefficient of resonant frequency were 15.5, 74380GHz, and -70ppm/$^{\circ}C$, respectively In order to modify the dielectric properties and densification temperature, B$_2$O$_3$ and V$_2$O$_{5}$ were added to ZnWO$_4$. 40 mol% B$_2$O$_3$ addition reduced the dielectric constant from 15.5 to 12. And the temperature coefficient of resonant frequency was improved from -70 to -7.6ppm/$^{\circ}C$. However, sintering temperature did not change due to either lack of liquid phase or high viscosity of liquid phase. Incorporation of small amount of V$_2$O$_{5}$ in ZnWO$_4$-B$_2$O$_3$ system enhanced liquid phase sintering. 0.lwt% V$_2$O$_{5}$ addition to the 0.6ZnWO$_4$-0.4B$_2$O$_3$ system, reduced the sintering temperature down to 95$0^{\circ}C$ Dielectric constant, quality factor, and temperature coefficient of resonant frequency were 9.5, 16737GHz, and -21.6ppm/$^{\circ}C$ respectively.ively.

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Research of an On-Line Measurement Method for High-power IGBT Collector Current

  • Hu, Liangdeng;Sun, Chi;Zhao, Zhihua
    • Journal of Power Electronics
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    • v.16 no.1
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    • pp.362-373
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    • 2016
  • The on-line measurement of high-power IGBT collector current is important for the hierarchical control and short-circuit and overcurrent protection of its driver and the sensorless control of the converter. The conventional on-line measurement methods for IGBT collector current are not suitable for engineering measurement due to their large-size, high-cost, low-efficiency sensors, current transformers or dividers, etc. Based on the gate driver, this paper has proposed a current measuring circuit for IGBT collector current. The circuit is used to conduct non-intervention on-line measurement of IGBT collector current by detecting the voltage drop of the IGBT power emitter and the auxiliary emitter terminals. A theoretical analysis verifies the feasibility of this circuit. The circuit adopts an operational amplifier for impedance isolation to prevent the measuring circuit from affecting the dynamic performance of the IGBT. Due to using the scheme for integration first and amplification afterwards, the difficult problem of achieving high accuracy in the transient-state and on-state measurement of the voltage between the terminals of IGBT power emitter and the auxiliary emitter (uEe) has been solved. This is impossible for a conventional detector. On this basis, the adoption of a two-stage operational amplifier can better meet the requirements of high bandwidth measurement under the conditions of a small signal with a large gain. Finally, various experiments have been carried out under the conditions of several typical loads (resistance-inductance load, resistance load and inductance load), different IGBT junction temperatures, soft short-circuits and hard short-circuits for the on-line measurement of IGBT collector current. This is aided by the capacitor voltage which is the integration result of the voltage uEe. The results show that the proposed method of measuring IGBT collector current is feasible and effective.

Proposal of a piezoelectric floating mass transducer for implantable middle ear hearing devices (이식형 인공중이를 위한 압전 플로팅 매스 트랜스듀서의 제안)

  • Lee, Chang-Woo;Kim, Min-Kyu;Park, Il-Yong;Song, Byung-Seop;Roh, Yong-Rae;Cho, Jin-Ho
    • Journal of Sensor Science and Technology
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    • v.14 no.5
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    • pp.322-330
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    • 2005
  • A new type of transducer, piezoelectric floating mass transducer (PFMT) which has advantages of piezoelectric and electromagnetic transducer has been proposed and implemented for the implantable middle ear hearing devices. By the uneven bonding of piezoelectric material to the inner bottom of transducer case, the PFMT can vibrate back-and-forth along the longitudinal axis of the transducer even though the piezoelectric material within the cylindrical case produces only the bilateral expansion and contraction according to the applied electrical signal. To improve efficiency of the PFMT, the multi-layered piezoelectric material has been adapted. The small number of components in the PFMT enables the simple manufacturing and the easy implanting into the middle ear. In order to examine the characteristics of vibration, mechanical modeling and finite element analyses of the proposed transducer have been performed. From the result of theoretical analyses and the measured data from the experiment, it is verified that the implemented PFMT can be used in implantable middle ear hearing devices.

A Design of DLL(Delay-Locked-Loop) with Low Power & High Speed locking Algorithm (저전력과 고속 록킹 알고리즘을 갖는 DLL(Delay-Locked LooP) 설계)

  • 경영자;이광희;손상희
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12C
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    • pp.255-260
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    • 2001
  • This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

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Estrus Synchronization and Pregnancy Rate Using Ovsynch Method in Uganda Dairy Farms (우간다 낙농가에서 Ovsynch 방법에 의한 발정동기화 및 수태율)

  • Kwon, Dae-Jin;Im, Seok Ki;Kim, Hyun;Lee, Hak-Kyo;Song, Ki-Duk
    • Journal of Embryo Transfer
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    • v.32 no.3
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    • pp.159-163
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    • 2017
  • The artificial insemination (AI) is one of the best assisted reproductive technologies for increasing reproductive capacity and facilitating the genetic improvement in farm animals. AI has been used in Uganda for over 60 years, but a small population of the total herd has been used. This study was conducted to investigate the efficacy of AI with estrus synchronization technique and to propose ways of improving the productivity of dairy farms through AI services in Uganda. In total, 78 cows from 11 dairy farms were selected for timed-AI. Synchronization was performed according to the ovsynch programs followed by AI using frozen semen from Korean Holstein (0.5 ml straws). Pregnancy rate was varying among farms (0-50%) and the overall pregnancy rate was 28.2%. Cows in luteal phase at the time of treatment was 40.0% whereas that in follicular phase was 20.8%. After treatment, cows that showed normal estrus signal were 45.5% (25/55). Abnormal estrus was categorized into pre-estrus (9.1%), cystic ovaries (21.8%), anestrus (18.2%) and delayed ovulation (5.5%), respectively. These results imply that an assured protocol for timed-AI should be developed to improve the productivity of dairy farms through AI services in Uganda.

An Experimental Study on Breaking Waves (쇄파 발생에 관한 실험적 연구)

  • 이동연;주성문;최항순
    • Journal of Korean Society of Coastal and Ocean Engineers
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    • v.8 no.1
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    • pp.37-43
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    • 1996
  • Breaking waves were generated in a 2-D flume. A piston-type wavemaker was operated in accordance with signals which consist of elementary harmonics with appropriate phase differences. These phase differences were estimated by using a linear wave theory so that wave crests were to be concentrated at the same position. The stroke of wavemaker was controlled to create plunging-type breaking waves. The signal with small amplitude could not generate breaking waves. In the case of moderate amplitudes, various breaking waves could be obtained. Most of breaking waves were spilling type. Only when the wavemaker was operated with appropriate amplitude, plunging-type breaking waves were generated. The parameters of breaking waves are the wave steepness and the frequency bandwidth. If the central frequency was low, breaking waves were not generated. Based on experimental data, we found that the wave height of breaking inception was H = 0.0113 gT$^2$. We also made computations by using a mixed Euler-Lagrangian scheme under the assumption of potential flow. The numerical results show good agreements with tank measurements.

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