• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.3
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• pp.56-63
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• 1999

In this paper, we realize the active PFC(Power Factor Correction) system of BF (Boost Forward) converter with PWM-PFM control technique to control DC output voltage, and to control the input current with sinusoidal wave synchronized by the converter and inverter using power switching element, FET and IGBT. The control circuit of the suggested Boost converter is implemented with a microprocessor 80C196. After making the ratio of output voltage to current as 50V/1A and the duty ratio greater than 0.5. When input voltage is 30V and boost inductance is 1.1mH. We control the voltage changing rate according to the variation of load resistance using a PWM-PFM control technique. And finally we prove experimentally. PF can be improved up to 0.96 using the current shaping technique.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.291-297
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• 2012

Recently, Switching devices become cheaper, depending on the multi-level inverters are considered as the power-conversion systems for high-power and power-quality demanding applications. The multi-level inverters can reduce the THD(Total Harmonic Distortion) as the output which is similar sinusoidal waveform by synthesizing several capacitor DC voltages. However it has some disadvantages such as increased number of components, complex PWM control method. Therefore, this paper is proposed the new multi-level inverter topology using an new H-bridge output stage with a bidirectional auxiliary switch. The proposed topology is the 4-level 3-phase PWM inverter with less switching part than conventional multi-level inverters and reactive power control possible. In order to understand the new multi-level inverter, topology analysis and switching patterns and modes according to the current loop are described in this paper. The proposed multi-level inverter topology is validated through PSIM simulation and the experimental results are provided from a prototype.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.3
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• pp.56-61
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• 2007

In this paper, a circulating current reduction approach for the parallel operation of fuelcell systems with Z-source inverters is investigated. The carrier phase shifted SPWM(Sinusoidal Pulse Width Modulation) is used as a modulation method since it has an advantage in reducing output current harmonics. However, when this technique is applied to the parallel operation of Z-source inverters, it additionally produces circulating currents. A coupled circulating current reactor is used to reduce circulating current generated by the parallel operation of Z-source inverters and to reduce output current harmonics. The proposed circulating current reduction approach using coupled circulating current reactors is verified through simulation and experiment.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.52-57
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• 1999

It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.5
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• pp.443-449
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• 2005

In this paper, parallel operation systems with Z-source Inverters for the fuel cell systems are discussed. The carrier phase shifted SPWM(Sinusoidal Pulse Width Modulation) has an advantage in reducing harmonics of output current. However when this technique applies in parallel operation of Z-source inverters, it additionally produces circulating currents. The circulating current is analyzed and a method to prevent the circulating current is applied to the parallel operation systems of Z-source inverters. To maintain high performance with reduced circulating current in inverter output and low harmonic components in load current, circulating current reactors are used. The proposed approach is verified through simulation and experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.4
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• pp.322-331
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• 2002

In this paper, a single-phase to three-phase PWM converter topology using a single-phase half-bridge PWM rectifier and a 2-leg inverter for low cost three-phase induction motor drives is proposed. In addition, the source voltage sensor is eliminated with a state observer which controls the deviation between the model current and the system current to be zero. The converter topology is of lower cost than the conventional one, which gives sinusoidal input current, unity power factor, dc output voltage control, bidirectional power flow and VVVF output voltage. The experimental results for V/F control of 3Hp induction motor drives have been shown.

• Journal of Power Electronics
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• v.18 no.2
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• pp.407-417
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• 2018

A novel family of Buck mode three-level direct ac converters with a high frequency link is proposed. These converters can transfer an unsteady high ac voltage with distortion into a regulated sinusoidal voltage with a low THD at the same frequency. The circuit configuration is constituted of a three-level converter, high frequency transformer, cycloconverter, as well as input and output filters. The topological family includes forward, push-pull, half-bridge, and full-bridge modes. In order to achieve a reliable three-level ac-ac conversion, and to overcome the surge voltage and surge current of the cycloconverter, a phase-shifted control strategy is introduced in this paper. A prototype is presented with experimental results to demonstrate that the proposed converters have five advantages including high frequency electrical isolation, lower voltage stress of the power switches, bi-directional power flow, low THD of the output voltage, and a higher input power factor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.