• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.229.1-229.1
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• 2014

Tactile sensors have widely been researched in the areas of electronics, robotic system and medical tools for extending to the form of bio inspired devices that generate feeling of touch mimicking those of humans. Recent efforts in adapting the tactile sensor have included the use of novel materials with both scalability and high sensitivity [1]. Graphene, a 2-D allotrope of carbon, is a prospective candidate for sensor technology, having strong mechanical properties [2] and flexibility, including recovery from mechanical stress. In addition, its truly 2-D nature allows the formation of continuous films that are intrinsically useful for realizing sensing functions. However, very few investigations have been carrier out to investigate sensing characteristics as a device form with the graphene subjected to strain/stress and pressure effects. In this study, we present a sensor of vertical forces based on single-layer graphene, with a working range that corresponds to the pressure of a gentle touch that can be perceived by humans. In spite of the low gauge factor that arises from the intrinsic electromechanical character of single-layer graphene, we achieve a resistance variation of about 30% in response to an applied vertical pressure of 5 kPa by introducing a pressure-amplifying structure in the sensor. In addition, we demonstrate a method to enhance the sensitivity of the sensor by applying resistive single-layer graphene.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.22-31
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• 2015

Recently, 3rd Generation Partnership Project (3GPP) has developed device-to-device (D2D) communication to cope with the explosively increasing mobile data traffic. The D2D communication uses sidelink based on single carrier-frequency division multiple access (SC-FMDA) due to its low peak-to-average power ratio (PAPR). In addition, demodulation reference signal (DMRS) is designed to support multiple input multiple output (MIMO). In this paper, we propose the DFT-based channel estimation scheme for sidelink in D2D communication. The proposed scheme uses the 2-Dimensional Minimum Mean Square Error (2-D MMSE) interpolation scheme for the user moving at a high speed. We perform the system level simulation based on 20MHz bandwidth of 3GPP LTE-Advanced system. Simulation results show that the proposed channel estimation scheme can improve signal-to-interference-plus-noise ratio (SINR), throughput and spectral efficiency of conventional scheme.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.63-63
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• 2010

Ability to transport extracted carriers from NQDs is essential for the development of most NQD based applications. Strategies to facilitate carrier transport while preserving NQDs' optical characteristics include: 1) Fabricating neat films of NQDs with modified surfaces either by adapting series of ligands with certain limitations or by applying physical processes such as heat annealing 2) Coupling of NQDs to one-dimensional nanostructures such as single walled carbon nanotubes (SWNTs) or various types of nanowires. NQD-nanowire hybrid nanostructures are expected to facilitate selective wavelength absorption, charge transfer to 1-D nanostructures, and efficient carrier transport. Even with the vast interests in using NQD-SWNT hybrid materials in optoelectric applications, still, no reports so far have clearly elucidated the optoelectric behavior when they were assembled on the FET mainly because the complexity involving in both components in their preparation and characterization. We have monitored the optical properties of both components (NQDs, SWNTs) from the synthesis, to the assembly, and to the device. More importantly, by using pyridine molecules as a linker to non-covalently attach NQDs to SWNTs, we were able to assemble NQDs on SWNTs with precise density control without harming their electronic structures. Furthermore, by measuring electrical signals from the fabricated aligned SWNTs-FET using dielectrophoresis (DEP), we were able to elucidate the charge transfer mechanism.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.485-485
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• 2009

Double side polishing process has been used for various industrial applications, such as polishing of semiconductor substrates and flat panel display glasses. In wafer manufacturing, double side polishing process is applied to improve wafer flatness and to minimize particle generation from wafers in device manufacturing processes, which is recognized as one of the most important processes. Whereas the kinematical modeling and analysis results of single side polishing, extensively used for chemical-mechanical polishing (CMP) in device manufacturing, are well investigated, the studies in conjunction with double side polishing are barely carried out, due to the complication of polishing system and the uncertainty of wafer motion in the carrier. This paper suggests the derivation of kinematical model with consideration of carrier and wafer motion in double side polishing, and then presents the effect of kinematical parameters on material removal amount and its non-uniformity. The kinematical analysis results help to understand the double side polishing process and to control the polishing results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.185-190
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• 2016

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.234-235
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• 2008

The surface flatness of heteroepitaxially grown 3C-SiC thin films is a key factor affecting electronic and mechanical device applications. This paper describes the surface flatness of poly(polycrystalline) 3C-SiC thin films according to Ar flow rates and the geometric structures of reaction tube, respectively. The poly 3C-SiC thin film was deposited by APCVD (Atmospheric pressure chemical vapor deposition) at $1200^{\circ}C$ using HMDS (Hexamethyildisilane : $Si_2(CH_3)_6)$ as single precursor, and 1~10 slm Ar as the main flow gas. According to the increase of main carrier gas, surface fringes and flatness are improved. It shows the distribution of thickness is formed uniformly.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.333-337
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• 2004

This paper describe a design of 5GHz OFDM baseband chip for IEEE 802.11a wireless LAN. The proposed device is consists of transmitter and receiver within a single FPGA chip. We applied single tap equalizer that use Normalized LMS algorithm to remove ISI that happen at high speed data transmission. And also, we used carrier wave frequency offset algorithm that use training symbol to remove ICI. The simulation results show the correct transmission without errors the between transmitter and receiver And we can remarkably reduce the number of register through the synthesized circuits by using DSP block and EMB(Embedded Memory Block). The target device for implementation of the synthesized circuits is Altera Stratix EPIS25FC672 FPGA and design platform is VHDL.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.986-995
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• 2011

In this paper, we propose a noise whitening decision feedback equalizer for single carrier frequency division multiple access (SC-FDMA) receivers. SC-FDMA has the same advantage as that of orthogonal frequency division multiple access (OFDMA) in which the multipath effect can be removed easily, and also solves the problem of high peak to average power ratio (PAPR) which is the main drawback of OFDMA. Although SC-FDMA is a single carrier transmission scheme, a simple frequency domain linear equalizer (FD-LE) can be implemented as in OFDMA, which can dramatically reduce the equalizer complexity. Moreover, some residual intersymbol interference in the output of the FD-LE can be further removed by an additional nonlinear decision feedback equalizer (DFE) in time domain, because the time domain signal is a digitally modulated symbol. In the conventional DFE, however, the noise is not white at the input of the decision device and correspondingly the decision is not optimum. In this paper, we propose an improved DFE scheme for SC-FDMA systems where a linear noise whitening filter is inserted before the decision device of the conventional DFE scheme. Through computer simulations, we compare the bit error rate performance of the proposed DFE scheme with the conventional equalizers.