• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.12
• /
• pp.108-115
• /
• 2014

Recently, Uninterruptible power supply(UPS) is spotlighted from concern about black out, due to reserve power problem caused by increased power consumption. When fault occurs on the grid, UPS system supplies power to loads instead of the grid. Also, it is an advantage of possible operation as Energy storage system(ESS). Bi-directional power control of AC/DC Pulse width modulation(PWM) converter is essential for grid-connected UPS system. And, mode transfer control has to be performed considering phase and dynamic characteristic under grid condition. In this paper, control of mode transfer and bi-directional power control of AC/DC PWM converter is proposed for UPS system. Also, it is verified by simulation and experimental results.

• Journal of Power Electronics
• /
• v.16 no.3
• /
• pp.1097-1109
• /
• 2016

Fault detection and isolation are related to system monitoring, identifying when a fault has occurred, and determining the type of fault and its location. Fault detection is utilized to determine whether a problem has occurred within a certain channel or area of operation. Fault detection and diagnosis have become increasingly important for many technical processes in the development of safe and efficient advanced systems for supervision. This paper presents an integrated technique for fault diagnosis and classification for open- and short-circuit faults in three-phase inverter circuits. Discrete wavelet transform and principal component analysis are utilized to detect the discontinuity in currents caused by a fault. The features of fault diagnosis are then extracted. A fault dictionary is used to acquire details about transistor faults and the corresponding fault identification. Fault classification is performed with a fuzzy logic system and relevance vector machine (RVM). The proposed model is incorporated with a set of optimization techniques, namely, evolutionary particle swarm optimization (EPSO) and cuckoo search optimization (CSO), to improve fault detection. The combination of optimization techniques with classification techniques is analyzed. Experimental results confirm that the combination of CSO with RVM yields better results than the combinations of CSO with fuzzy logic system, EPSO with RVM, and EPSO with fuzzy logic system.

• Progress in Superconductivity and Cryogenics
• /
• v.20 no.2
• /
• pp.34-39
• /
• 2018

A cryogenic cooling system is designed for a 154 kV/ 2 kA three-phase hybrid type superconducting fault current limiter (SFCL). The superconducting modules of the SFCL have the operating condition of 71 K at 500 kPa. The total heat load of the SFCL including the cooling system is estimated at 9.6 kW. The cooling system of the closed loop is configured to meet the operating condition, depending on cooling methods of forced flow cooling and re-liquefaction cooling. The cooling system is composed of three cryostats with superconducting modules, cryocoolers, liquid nitrogen circulation pumps, a subcooler and a pressure builder. The basic cooling concept is to circulate liquid nitrogen between three SFCL cryostats and the cryocooler, while maintaining the operating pressure. The design criterion for the cooling system is based on the operation results of the cooling system for a 154 kV/2 kA single-phase hybrid SFCL. The specifications of system components including the piping system are determined according to the design criterion.

• Journal of Power Electronics
• /
• v.18 no.1
• /
• pp.116-128
• /
• 2018

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.7
• /
• pp.1193-1203
• /
• 2016

This paper proposes a droop control scheme to compensate the unbalanced line-to-line voltage of unbalanced 3-phase load which is coupled with two inverter-based distributed generations through unequal impedance lines. Unbalanced line-to-line load voltages occur due to using single-phase loads, which brings about bad effects on the coupled inverters and the distributed generations. In order to compensate the unbalanced line-to-line voltages, a positive sequence voltage control was used for sharing the active and reactive power and a negative sequence control was used for reducing the negative sequence voltage. The feasibility of the proposed scheme was first verified by computer simulations, and then experiments with a hardware set-up built in the lab. The experimental results were compared with the simulation results to confirm the feasibility of the proposed scheme.

• Journal of the Korean Society of Safety
• /
• v.34 no.3
• /
• pp.102-110
• /
• 2019

This paper describes the work and results of the preliminary Probabilistic Safety Assessment (PSA) for a research reactor in the design phase. This preliminary PSA was undertaken to assess the level of safety for the design of a research reactor and to evaluate whether it is probabilistically safe to operate and reliable to use. The scope of the PSA described here is a Level 1 PSA which addresses the risks associated with core damage. After reviewing the documents and its conceptual design, eight typical initiating events are selected regarding internal events during the normal operation of the reactor. Simple fault tree models for the PSA are developed instead of the detailed model at this conceptual design stage. A total of 32 core damage accident sequences for an internal event analysis were identified and quantified using the AIMS-PSA. LOCA-I has a dominant contribution to the total CDF by a single initiating event. The CDF from the internal events of a research reactor is estimated to be 7.38E-07/year. The CDF for the representative initiating events is less than 1.0E-6/year even though conservative assumptions are used in reliability data. The conceptual design of the research reactor is designed to be sufficiently safe from the viewpoint of safety.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.19 no.2
• /
• pp.157-163
• /
• 2014

This paper proposes a two-stage step-down buck and a tapped-inductor boost cascaded converter for high efficiency photovoltaic micro-inverter applications. The proposed inverter is a new structure to inject a rectified sinusoidal current into a low-frequency switching inverter for single-phase grid with unity power factor. To build a rectified-waveform of the output current. the converter employs both of a high efficiency step-up and a step-down converter in cascade. In step-down mode, tapped inductor(TI) boost converter stops and the buck converter operates alone. In boost mode, the TI converter operates with the halt of buck operation. The converter provides a rectified current to low frequency inverter, then the inverter converts the current into a unity power-factor sinusoidal waveform. By applying a TI, the converter can decrease the turn-on ratios of the main switch in TI boost converter even with an extreme step-up operation. The performance validation of the proposed design is confirmed by an experimental results of a 120W hardware prototype.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.3B no.1
• /
• pp.44-51
• /
• 2003

The module UPS can flexibly implement expansion of power system capacities. Further-more, it can be used to build up the parallel redundant system to improve the reliability of power system operation. To realize the module UPS, load sharing without interconnection among parallel connecting modules as well as a small scale and lightweight topology is necessary. In this paper, the three-arm converter/inverter is compared with the general full-bridge and half-bridge topology from a practical point of view and chosen as the module UPS topology. The switching control approaches based on a pulse width modulation of the converter and inverter of the system are presented independently. The frequency and voltage droop method is applied to parallel operation control to achieve load sharing. Two prototype 3㎸A modules are designed and implemented to confirm the effectiveness of the pro-posed approaches. Experimental results show that the three-arm UPS system has a high power factor, a low distortion of output voltage and input current, and good load sharing characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.12
• /
• pp.1055-1061
• /
• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.15 no.3
• /
• pp.244-251
• /
• 2010

High speed motors have been widely used in industries to reduce system size and improve power conversion efficiency. However, the high speed motors sometimes suffer from core losses caused by PWM current ripple; noting that the phase inductance, $L_s$, of high speed motor is smaller than that of ordinary motors. In the proposed topology, three PWM inverters are connected in parallel through nine coupled inductors. Compared to the PWM current ripple of the conventional single inverter system, that of the proposed scheme can be conspicuously reduced without the voltage drop at the inductors. In this paper a theoretical analysis of the output voltage of the proposed topology is presented, and then the validity of the proposed method is verified by experimental results.