• Title/Summary/Keyword: Single Event Upset (SEU)

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SEU Mitigation Strategy and Analysis on the Mass Memory of the STSAT-3 (과학기술위성 3호 대용량 메모리에서의 SEU 극복 및 확률 해석)

  • Kwak, Seong-Woo
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.4
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    • pp.35-41
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    • 2008
  • When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

Design of Radiation Hardened Shift Register and SEU Measurement and Evaluation using The Proton (내방사선용 Shift Register의 제작 및 양성자를 이용한 SEU 측정 평가)

  • Kang, Geun Hun;Roh, Young Tak;Lee, Hee Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.121-127
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    • 2013
  • Memory devices including SRAM and DRAM are very susceptible to high energy radiation particles in the space. Abnormal operation of the devices is caused by SEE or TID. This paper presents a method to estimate proton SEU cross section representing the susceptibility of the latch circuit that the unit cell of the SRAM and proposes a new latch circuit to mitigate the SEU. 50b shift register was fabricated by using the conventional latch and the proposed latch in $0.35{\mu}m$ process. Irradiation experiment was conducted at KIRAMS by using 43MeV proton beam. It was found that the proposed latch-shift register is not affected by the radiation environment compared to the conventional latch-shift register.

CRE ECPERIMENT OF KITSAT-1 (우리별 1호에서의 SPACE RADIATION 환경 조사)

  • 신영훈;민경욱;최영완;김성헌
    • Journal of Astronomy and Space Sciences
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    • v.11 no.1
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    • pp.131-145
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    • 1994
  • The Cosmic Ray Experiment (CRE) is one of the modules flown on board the KITSAT-1 satellite and consistes of two sub-systems: the Total Dose Experiment (TDE) and the Cosmic Particl Experiment(CPE). The purpose of CRE is to characterize the space radiation environment as encountered by an Earth-orbiting spacecraft. KITSAT-1 orbit is dominated by the inner Van Allen radiation belt. This region has a large population of high energy protons which contributes significantly to both long-term and transient radiation effects. The data shows that the inner Van Allen radiation belt is very stable and the solar activity influences the CPE, TDE data and SEU(Single Event Upset) rates. The result also shows that much larger high energy particle flux is recorded than the predictions of the CREME code.

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HAUSAT-2 SATELLITE RADIATION ENVIRONMENT ANALYSIS AND SOFTWARE RAMMING CODE EDAC IMPLEMENTATION (HAUSAT-2 위성의 방사능 환경해석 및 소프트웨어 HAMMING CODE EDAC의 구현에 관한 연구)

  • Jung, Ji-Wan;Chang, Young-Keun
    • Journal of Astronomy and Space Sciences
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    • v.22 no.4
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    • pp.537-558
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    • 2005
  • This paper addresses the results of HAUSAT-2 radiation environment and effect analyses, including TID and SEE analyses. Trapped proton and electron, solar proton, galactic cosmic ray models were considered for HAUSAT-2 TID radiation environment analysis. TID was analyzed through total dose-depth curve and the radiation tolerance of TID for HAUSAT-2 components was verified by using DMBP method and sectoring analysis. HAUSAT-2 LET spectrum for heavy ion and proton were also analyzed for SEE investigation. SEE(SEU, SEL) analyses were accomplished for MPC860T2B microprocessor and K6X8008T2B memory. It was estimated that several SEUs may occur without SEL during the HAUSAT-2 mission life(2 years). Software Hamming Code EDAC has been implemented to detect and correct the SEU. In this study, all radiation analyses were conducted by using SPENVIS software.

Soft error correction controller for FPGA configuration memory (FPGA 재구성 메모리의 소프트에러 정정을 위한 제어기의 설계)

  • Baek, Jongchul;Kim, Hyungshin
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5465-5470
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    • 2012
  • FPGA(Field Programmable Gate Array) devices are widely used due to their merits in circuit development time, and development cost. Among various FPGA technologies, SRAM-based FPGAs have large cell capacity so that they are attractive for complex circuit design and their reconfigurability. However, they are weak in space environment where radiation energy particles cause Single Event Upset(SEU). In this paper, we designed a controller supervising SRAM-based FPGA to protect configuration memory inside. The controller is implemented on an Anti-Fusing FPGA. Radiation test was performed on the implemented computer board and the result show that our controller provides better SEU-resilience than TMR-only system.

Radiation에 의한 SEU 오류 검출 및 수정 방안 소개

  • Yang, Seung-Eun;Sin, Hyeon-Gyu;Choe, Jong-Uk;Cheon, Lee-Jin
    • The Bulletin of The Korean Astronomical Society
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    • v.37 no.2
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    • pp.181.2-181.2
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    • 2012
  • 우주공간에서는 solar particle과 galactic cosmic ray에 포함된 proton, electron 및 heavy ion등에 의해 radiation 현상이 발생하는데 이는 각종 전자장비의 성능 감쇄 및 디지털 장비의 내부 정보를 교란을 야기할 수 있다. 특히 메모리의 bit 정보가 반전되는 Single Event Upset (SEU)의 경우 인공위성 및 우주정거장 등의 시스템에서도 빈번히 발생할 수 있으며 적절한 조치가 이루어지지 않으면 주어진 임무 수행 실패는 물론 시스템 failure까지 이를 수 있다. 따라서 SEU에 의한 문제 발생 시 신속한 문제 확인 및 대처가 매우 중요하다. 본 논문에서는 SEU의 발생 원인 및 영향과 기존의 오류 검출 및 수정 기법에 대해 소개하도록 한다. 또한 효율적이고 신뢰성 있는 설계를 위해 각 하드웨어 소자 특성에 따른 적합한 SEU 회피 방안을 제시하도록 한다.

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비동기 디지털 시스템의 고장 진단 및 극복 기술 동향

  • Gwak, Seong-U;Yang, Jeong-Min
    • ICROS
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    • v.17 no.4
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    • pp.35-41
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    • 2011
  • 비동기적으로 동작하는 디지털 회로는 동기 순차 회로에 비해서 고속, 저전력 소비 등 여러 가지 장점을 지니기 때문에 현대 디지털 시스템에서 여전히 중요한 요소로 사용되고 있다. 본 기고에서는 비동기 순차 회로에서 발생하는 고장을 진단하고 극복하는 최신 기술을 소개한다. 본 기고에서 주로 다루는 기술은 '교정 제어'로서 피드백 제어의 원리를 이용하여 비동기 순차 회로의 안정 상태를 바꾸는 기법이다. 크리티컬 레이스(critical race), 무한 순환 등 비동기 회로 설계상의 오류를 포함하여 SEU(Single Event Upset), 총이론화선량(TID)에 의한 고장 등 외부 환경에 의해서 발생하는 비동기 회로의 고장을 교정 제어를 이용하여 진단하고 극복하는 기술에 대해서 알아본다.

Engineering Model Design and Implementation of Mass Memory Unit for STSAT-2 (과학기술위성 2호 대용량 메모리 유닛 시험모델 설계 및 구현)

  • Seo, In-Ho;Ryu, Chang-Wan;Nam, Myeong-Ryong;Bang, Hyo-Choong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.33 no.11
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    • pp.115-120
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    • 2005
  • This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

A Study on Fault Detection Scheme on TMRed Circuits (삼중화된 회로에서의 결함 감지를 위한 방법에 관한 연구)

  • Kang, Dong-Soo;Lee, Jong-Kil;Jhang, Kyoung-Son
    • Proceedings of the Korean Information Science Society Conference
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    • 2011.06b
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    • pp.313-316
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    • 2011
  • SRAM-based FPGAs are very sensitive to single event upset(SEU) induced by space irradiation. To mitigate SEU effects, space applications employ some mitigation schemes. The triple modular redundancy(TMR) is a well-known mitigation scheme. It uses one or three voters as well as three identical blocks performing the same work. The voters can mask out one error in the outputs from the three replicated blocks. One SEU error in TMRed circuits can be masked but it needs to be detected for some reasons such as to analyze the SEU effects in the satellite or to recover the circuits from the error before additional error occur. In this paper, we developed a fault detection circuit and reporting system to detect a fault on the TMRed circuits. To verify our error detection circuit and reporting circuit, we performed an irradiation test at MC-50 Cyclotron. Experimental results showed that error detection circuit can detect a fault on the TMRed test circuit in radiation environment.

Development of Error-Corrector Control Algorithm for Automatic Error Detection and Correction on Space Memory Modules (우주용 메모리의 자동 오류극복을 위한 오류 정정기 제어 알고리즘 개발)

  • Kwak, Seong-Woo;Yang, Jung-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.5
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    • pp.1036-1042
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    • 2011
  • This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.