• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.27 no.1
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• pp.152-157
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• 2003

Process design of hot forging, asymmetric to symmetric rib-web shape steel, which is used for the turnout of railway express has been investigated. Owing to the big difference in shape between the initial billet and the final forged product, it is impossible to hot forge the rail in a single step. Therefore, multi step forging as well as die design for each step are necessary for the production. The deformation behavior during hot forging has been analyzed by the numerical simulation through commercial FEA software, $DEFORM^{TM}$-2D. Modification of the design and repeated simulation have been carried out on the basis of the simulation result. For comparison with the simulation results. flow analysis experiment using plasticine has been also carried out. The results of the flow analysis experiment showed good agreement with those of the simulation. Therefore, the developed process design could be applied to the actual production.

• Journal of Powder Materials
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• v.21 no.1
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• pp.39-43
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• 2014

Bulk nanostructured copper was fabricated by a shock compaction method using the planar shock wave generated by a single gas gun system. Nano sized powders, average diameter of 100 nm, were compacted into the capsule and target die, which were designed to eliminate the effect of undesired shock wave, and then impacted with an aluminum alloy target at 400 m/s. Microstructure and mechanical properties of the shock compact specimen were analyzed using an optical microscope (OM), scanning electron microscope (SEM), and micro indentation. Hardness results showed low values (approximately 45~80 Hv) similar or slightly higher than those of conventional coarse grained commercial purity copper. This result indicates the poor quality of bonding between particles. Images from OM and SEM also confirmed that no strong bonding was achieved between them due to the insufficient energy and surface oxygen layer of the powders.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2707-2712
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• 2011

In this paper, a power factor correction (PFC) control circuit using single stage boundary conduction mode(BCM) for the 400V. 120W LED drive application has been designed. The proposed control circuit is aimed for improvement of the power factor correction and reduction of the total harmonic distortion. In this circuit, a new CMOS multiplier structure is used instead of a conventional BJT(bipolar junction transistor) based multiplier where has a relatively large area. The CMOS multiplier can bring 30 % reduced chip area, competitive die cost in comparison with the conventional BJT multiplier.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.79-86
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• 1994

Gain-guided broad-area single quantum well separate confinement heterostructure diode lasers have been fabricated from structures grown by metal organic vapor phase epitaxy. The active layer of the epi-structure is InGaAs emitting 962-965nm and the guiding layer GaAs. The channel width is fixed to 150${\mu}$m and the cavity length varys within the range of 300~800${\mu}$m. For uncoated LD's, the output power of 0.7W has been obtaained at a pulsed current level of 2A, which results about 60% external quantum efficiency. The threshold current density is 200A/cm$^{2}$ for the cavity lengths of 800.mu.m LD's. The stain effect upon the transparent current density has been observed. The internal quantum efficiency is expected to be 88% and the internal loss to be 18$cm^{-1}$. The beam divergence has been measured to be 7$^{\circ}$to lateral and 40$^{\circ}$to transverse direction. finally, 1.2W continuous-wave output power has been obtained at a current level of 2A for AR/HR coated LD's die-bonded on Cu heat-sink and cooled by TEC.

• Clinical and Experimental Reproductive Medicine
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• v.46 no.4
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• pp.206-210
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• 2019

Mucopolysaccharidosis type II (MPS II) is a rare X-linked recessive lysosomal storage disease caused by mutation of the iduronate-2-sulfatase gene. The mutation results in iduronate-2-sulfatase deficiency, which causes the progressive accumulation of heparan sulfate and dermatan sulfate in cellular lysosomes. The phenotype, age of onset, and symptoms of MPS II vary; accordingly, the disease can be classified into either the early-onset type or the late-onset type, depending on the age of onset and the severity of the symptoms. In patients with severe MPS II, symptoms typically first appear between 2 and 5 years of age. Patients with severe MPS II usually die in the second decade of life although some patients with less severe disease have survived into their fifth or sixth decade. Here, we report the establishment of a preimplantation genetic diagnosis (PGD) strategy using multiplex nested polymerase chain reaction, direct sequencing, and linkage analysis. Unaffected embryos were selected via the diagnosis of a single blastomere, and a healthy boy was delivered by a female carrier of MPS II. This is the first successful application of PGD in a patient with MPS II in Korea.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2006.05a
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• pp.377-380
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• 2006

Manufacturing process of Ti-6Al-4V alloy billet was investigated with FEM simulation and experimental analysis. Before the breakdown process of Ti-6Al-4V alloy ingot, FEM simulation for the breakdown processes of Ti-6Al-4V alloy ingot was used to calculate the forging load and state variables such as strain, strain rate and temperature. In order to breakdown the ingot structure and make an equiaxed structure billet, two different processes were employed for a VAR/VAR processed Ti-6Al-4V alloy ingot. Firstly, the ingot was cogged in single-phase $\beta$ field at the temperature of $1,100^{\circ}C$. In the process, the coarse and inhomogeneous structure developed by the double melting process was broken down. The second breakdown was performed by upsetting and cogging processes in $\alpha+\beta$ phase field to obtain the microstructure of fine equixed $\alpha$ structure in the matrix of transformed $\beta$. Finally, the mechanical properties of Ti-6Al-4V alloy billet made in this work were compared with those of other billet and ring product.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.160-165
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• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).