• 한국통신학회논문지
• /
• 제40권12호
• /
• pp.2503-2510
• /
• 2015

본 논문에서는 전력 정보를 측정하기 위한 단상 에너지 측정용 IC의 구현 방법을 제안한다. 제안된 전력 측정용 IC는 2개의 PGA(Programmable Gain Amplifier), 2개의 ${\sum}{\Delta}$ modulator, reference 회로, LDO(Low-dropout) regulator, 온도 센서, 필터부, 계산 엔진, 보정 제어부, 레지스터, 외부 인터페이스로 구성된다. $0.18-{\mu}m$ CMOS 공정으로 제작되었고, 32-pin QFN package로 제작되었다. 구현된 IC는 3.3V 전원을 공급받아 동작하며, 동작 클럭 주파수는 4,096 kHz이고, IC 동작시 소비 전력은 10 mW이다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.249-250
• /
• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• 전력전자학회논문지
• /
• 제13권6호
• /
• pp.453-460
• /
• 2008

본 논문은 중용량에 적합한 새로운 이중출력 LLC 공진형 DC/DC 컨버터에 관한 것으로써, 별도의 Post-regulator및 추가되는 제어 IC 없이 정밀한 이중출력이 가능한 새로운 방식의 컨버터를 제안한다. 제안된 컨버터의 제어방식은 펄스폭 변조(PWM)와 동시에 주파수 변조(PFM)를 통해 이루어지며 Master 와 Slave 출력을 각각 주파수, 듀티로 제어함으로써 Slave 출력을 위한 별도의 Post-Regulator 및 제어 IC가 필요 없기 때문에, 저가의 컨버터 구현이 가능하다. 또한 기존 LLC 공진형 DC/DC 컨버터와 같이 스위칭 소자의 영전압 스위칭이 보장되는 동시에, Post-Regulator 로 인한 손실이 없기 때문에 효율 및 발열 특성이 매우 우수하다. 본 논문에서는 제안된 컨버터의 우수성과 신뢰성 검증을 위해, 실제로 50" FHD급 PDP용 전원회로를 위한 시뮬레이션 검토 및 시작품을 제작하고 이를 이용한 실험결과를 바탕으로 제안된 컨버터의 타당성을 검증한다.

• 한국전자파학회논문지
• /
• 제29권8호
• /
• pp.632-639
• /
• 2018

본 논문에서는 130 nm 공정을 이용한 Ku-band에서의 송수신 칩을 사용하여 제작된 단일 안테나 모듈을 제안한다. 레이다 수신부에서 DCOC 피드백을 사용한 STC(sensitivity time control)가 거리에 따라 일정한 SNR을 유지한다. 또한 수신부 RF단에서 gain control을 통하여 수신단의 dynamic range를 조절할 수 있다. 칩의 출력 파워는 9 dBm이고, 수신부의 총 이득은 82 dB이다. 단일 안테나에서 Tx 신호가 Rx로 직접 누설되는 것을 막기 위해 stub-tuned hybrid coupler를 사용하였다. 최대 측정거리는 6 m이고, 혼안테나와 금속판을 사용하여 측정하였다.

• The Plant Pathology Journal
• /
• 제31권1호
• /
• pp.12-24
• /
• 2015

Rice Blast is the most devastating disease causing major yield losses in every year worldwide. It had been proved that using resistant rice varieties would be the most effective way to control this disease. Molecular screening and genetic diversities of major rice blast resistance genes were determined in 192 rice germplasm accessions using simple sequence repeat (SSR) markers. The genetic frequencies of the 10 major rice blast resistance genes varied from 19.79% to 54.69%. Seven accessions IC337593, IC346002, IC346004, IC346813, IC356117, IC356422 and IC383441 had maximum eight blast resistance gene, while FR13B, Hourakani, Kala Rata 1-24, Lemont, Brown Gora, IR87756-20-2-2-3, IC282418, IC356419, PKSLGR-1 and PKSLGR-39 had seven blast resistance genes. Twenty accessions possessed six genes, 36 accessions had five genes, 41 accessions had four genes, 38 accessions had three genes, 26 accessions had two genes, 13 accessions had single R gene and only one accession IC438644 does not possess any one blast resistant gene. Out of 192 accessions only 17 accessions harboured 7 to 8 blast resistance genes.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.909-912
• /
• 2005

According to miniaturization trend of rehabilitation medical equipment such as hearing aid, study to replace previous complex system with semiconductor SOC (System-on-Chip) chip becomes lively. In this study, after investigating of existent hearing aid performance in circuit design approach, low electric power consuming, single power supply (1.4V battery) CMOSS OP AMP was designed. Analog circuit design tools such as Hspice and Cadence were used for circuit simulation and implementing layout design. This study shows technical methods particularly for layout design. The work is done in pmos and nmos active element layout design in addition to passive element design such as resister, capacitor and inductor.

• 전기학회논문지
• /
• 제61권9호
• /
• pp.1275-1282
• /
• 2012

This paper proposes the 16-channel LED Driver IC for Full color LED display system. The proposed LED driver IC in this paper can draw current independent of temperature and supply voltage in each channel. Current flow in the channel is configurable via an external resistor. LED brightness is adjusted by 12-Bit PWM(Pulse Width Modulation) and 8-Bit DC(Dot Correction). A real-time monitoring of IC temperature ($130^{\circ}C/150^{\circ}C$) and LED status (open/short) is provided by LED driver IC and the user can receive warning and get information on problems. A 16-channel LED driver IC is produced using 0.35 um BCD process and the size is $2.5mm{\times}2.5mm$. In this paper, channel current characteristic and channel current control function were measured in order to verify am embodied 16-channel LED driver IC by producing a single IC test board.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
• /
• pp.644-646
• /
• 2000

According to the deregulations of governments in the world. the power industries of United State and European nations are proceeding remote meter reading and remote load control. But the core technology of multifunctional electronic meter implemented by programmable one-chip IC, which can be the right answer of all the power industy's efforts is now still under development in the advanced countries. Implementation of smallest size, lowest price single-phase meter with features which enable distribution automation such as bidirectional communication, Remote load control, remote meter reading, remote credit assigment. Prepayment billing system.

• The Journal of Advanced Prosthodontics
• /
• 제14권4호
• /
• pp.223-235
• /
• 2022

PURPOSE. To compare the clinical outcomes of two types of implant restoration for posterior edentulous area, 3-unit bridge supported by 2 implants and 3 implant-supported splinted crowns. MATERIALS AND METHODS. The data included 127 implant-supported fixed restorations in 85 patients: 37 restorations of 3-unit bridge supported by 2 implants (2-IB), 37 restorations of 3 implant-supported splinted crowns (3-IC), and 53 single restorations (S) as controls. Peri-implantitis and mechanical complications that occurred for 14 years were analyzed by multivariable Cox regression model. Kaplan-Meier curves and the multivariable Cox regression model were used to analyze the success and survival of implants. RESULTS. Peri-implantitis occurred in 28.4% of 2-IB group, 37.8% of 3-IC group, and 28.3% of S control group with no significant difference. According to the implant position, middle implants (P2) of the 3-IC group had the highest risk of peri-implantitis. The 3-IC group showed a lower mechanical complication rate (7.2%) than the 2-IB (16.2%) and S control group (20.8%). The cumulative success rate was 52.8% in S (control) group, 62.2% in 2-IB group, and 60.4% in 3-IC group. The cumulative survival rate was 98.1% in S (control) group, 98.6% in 2-IB group, and 95.5% in 3-IC group. There was no significant difference in the success and survival rate according to the restoration type. CONCLUSION. The restoration type was not associated with the success and survival of implants. The risk of mechanical complications was reduced in 3 implant-supported splinted crowns. However, the middle implants of the 3 implant-supported splinted crowns had a higher risk of peri-implantitis.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권4호
• /
• pp.445-453
• /
• 2015

A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.