• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.183-190
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• 1997

We present competition protocols to speed up the execution of sequential programs on a network of shared workstations in the background by exploiting their wasted computing capacity, without interfering with processes of workstation owners. In order to argue that competition protocols are preferable to migration protocols in this situation, we derive the closed form solutions for the speedup of competition protocols and migration protocols, and simulate both of protocols under comparable overhead assumptions. Based on our analytic results and simulation results, we show that competitive execution is superior to process migration, and that competitive execution can finish sequential programs significantly faster than noncompetitive execution, especially when the foreground load is sufficiently high.

• Journal of the Korean Solar Energy Society
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• v.33 no.3
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• pp.1-8
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• 2013

In order to identify positive or negative effect of seawall on wind turbine, a wind tunnel experiment has been conducted with a 1/100 scaled-down model of Goonsan wind farm which is located in West coast along seawall. Wind speedup due to the slope of seawall contributed to about 3% increment of area-averaged wind speed on rotor-plane of a wind turbine which is anticipated to augment wind power generation. From the turbulence measurement and flow visualization, it was confirmed that there would be no negative effect due to flow separation because its influence is confined below wind turbine blades' sweeping height.

• Wind and Structures
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• v.19 no.2
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• pp.219-232
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• 2014

The characteristics of turbulent boundary layers over hilly terrain depend strongly on the hill slope and upstream condition, especially inflow turbulence. Numerical simulations are carried out to investigate the neutrally stratified turbulent boundary layer over two-dimensional hills. Two kinds of hill shape, a steep one with stable separation and a low one without stable separation, two kinds of inflow condition, laminar turbulent, are considered. An auxiliary simulation, based on the local differential quadrature method and recycling technique, is performed to simulate the inflow turbulence be imposed at inlet boundary of the turbulent inflow, which preserves very well in the computational domain. A large separation bubble is established on the leeside of the steep hill with laminar inflow, while reattachment point moves upstream under turbulent inflow condition. There is stable separation on the side of low hill with laminar inflow, whilw not turbulent inflow. Besides increase of turbulence intensity, inflow can efficiently enhance the speedup around hills. So in practice, it is unreasonable to study wind flow over hilly terrain without considering inflow turbulence.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.37-44
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• 1999

This paper report the implementation results of Monte Carlo numerical calculation for ion distributions in plasma dry etching chamber and of the surface evolution simulator using cell removal method for topographical evolution of the surface exposed to etching ion. The energy and angular distributions of ion across the plasma sheath were calculated by MC(Monte Carlo) algorithm. High performance MPP(Massively Parallel Processing) algorithm developed in this paper enables efficient parallel and distributed simulation with an efficiency of more than 95% and speedup of 16 with 16 processors. Parallelization of surface evolution simulator based on cell removal method reduces simulation time dramatically to 15 minutes and increases capability of simulation required enormous memory size of 600Mb.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.883-891
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• 1998

This paper proposes a scheme to exploit SIMD parallelism in the simulation of Cellular Automata models. The basic idea is to increase the utilization of an ALU in the underlying computer and to reduce simulation time by exploiting the parallelism. Thus, several cells are packed into a computer word and transit their state together. To show the performance of the proposed simulation scheme, two Cellular Automata models are simulated under three distinct hardware environments. The results show considerably high simulation speed-up for every case. Especially, the simulation speedup with the proposed simulation scheme reaches nearly 20 times in the best case.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.5-5
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• 1992

The DEVS(discrete event system specification) formalism describes a discrete event system in a hierarchical, modular form. DEVSIM++ is C++ based general purpose DEVS abstract simulator which can simulate systems to be modeled by the DEVS formalism in a sequential environment. We implement P-DEVSIM++ which is a parallel version of DEVSIM++. In P-DEVSIM++, the external and internal event of models can be processed in parallel. To process in parallel, we introduce a hierarchical distributed simulation technique and some optimistic distributed simulation techniques. But in our algorithm, the rollback of a model is localized itself in contrast to the Time Warp approach. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.59-63
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• 2008

The methods or algorithms which can accelerate simulation speed became of great importance, as the modeling and simulation methodology for discrete event systems is used in many areas such as model validation/verification and performance evaluation. This paper proposes a tool named, DEVSIF composer. The tool is made of an automated compiled simulation technology and it builds a new composed model which can be executed much fast by composing the component models together. Models are described by our new specification language DEVSIF, which is compatible with object-oriented language and supports representation of a hierarchical model structure. Experimental results demonstrates that DEVSIF composer enhances the simulation speed of a transformed DEVS model 5 times faster than that of the original ones in average.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.64-76
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• 1992

The DEVS(discrete event system specificaition) formalism specifies a discrete event system in a hierarchical, modular form. DEVSIM++ is a C++based general purpose DEVS abstract simulator which can simulate systems modeled by the DEVS formalism in a sequential environment. This paper describes P-DEVSIM++which is a parallel version of DEVSIM++ . In P-DEVSIM++, the external and internal event of DEVS models can by processed in parallel. For such processing, we propose a parallel, distributed optimistic simulation algorithm based on the Time Warp approach. However, the proposed algorithm localizes the rollback of a model within itself, not possible in the standard Time Warp approach. An advantage of such localization is that the simulation time may be reduced. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• ETRI Journal
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• v.43 no.3
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• pp.483-510
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• 2021

In computational biology, desired patterns are searched in large text databases, and an exact match is preferable. Classical benchmark algorithms obtain competent solutions for pattern matching in O (N) time, whereas quantum algorithm design is based on Grover's method, which completes the search in $O(\sqrt{N})$ time. This paper briefly explains existing quantum algorithms and defines their processing limitations. Our initial work overcomes existing algorithmic constraints by proposing the quantum-based combined exact (QBCE) algorithm for the pattern-matching problem to process exact patterns. Next, quantum random access memory (QRAM) processing is discussed, and based on it, we propose the QRAM processing-based exact (QPBE) pattern-matching algorithm. We show that to find all t occurrences of a pattern, the best case time complexities of the QBCE and QPBE algorithms are $O(\sqrt{t})$ and $O(\sqrt{N})$, and the exceptional worst case is bounded by O (t) and O (N). Thus, the proposed quantum algorithms achieve computational speedup. Our work is proved mathematically and validated with simulation, and complexity analysis demonstrates that our quantum algorithms are better than existing pattern-matching methods.