• IE interfaces
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• v.1 no.1
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• pp.49-62
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• 1988

This paper deals with the case study that determines the best operating system of a container terminal using computer simulation techniques. For the simulation, SIMAN simulation language is used. The simulation model developed circumvents the dimensional restrictions imposed by the SIMAN package. Non-terminating simulation experiments are conducted for the 90 days' work on the basis of operation practices of real terminals.

• Electrical & Electronic Materials
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• v.10 no.6
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• Journal of Welding and Joining
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• v.9 no.3
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• pp.41-51
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• 1991

The thermomechanical coupling phenomena in the resistance welding process is complicated due to interactions of mechanical, thermal and electrical factors. Although experimental investigations of resistance spot welding have been carried out, but there are a few by computer simulation. so the purpose of this research is to decrease the time and cost much required in experimental investigation by carrying out the analysis of the resistance spot welding process through computer simulation based on the finite element method. The tool used in the computer simulation is the commercial ANSYS program package. A two dimensional axisymetric model is used to simulate the resistance spot welding for two stainless steel sheets of equal thickness and parametric study is carried out for variable welding current, workpieces of unequal thickness and dissimilar materials. The results from the computer simulation are in good agreement with the experimental one. Through these results, such items as stress distribution, temperature profiles, thermal expansion and weld nugget formation are predicted. Reliability and applicability of finite element models have been demonstrated to simulate and to analyze the resistance spot welding process.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.317-336
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• 2006

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.71-85
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• 2001

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.11
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• pp.5117-5122
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• 2011

In this paper, thermal analysis simulation program by taking advantage of COMSOL Multiphysics, LED Module for the production of the most preferred package type, omitting the COH Type COB Type and board simulation of the thermal analysis is in progress. LED Module that passes through the Heat-sink of the simulation results, depending on the location of the COB Type Max. Approximately $78^{\circ}C$ ~ Min. Approximately $62^{\circ}C$, COH Type the Max. Approximately $88^{\circ}C$ ~ Min. Approximately $67^{\circ}C$ has been confirmed that the temperature stability. Compared with COB Type Max. AIthough temperature difference is about $10^{\circ}C$, Min. At a temperature of about $5^{\circ}C$ confirmed to be enough to reduce the gap, LED Point confirming the results of the temperature curves for COB Type Max. Approximately $100^{\circ}C$ ~ Min. Approximately $77^{\circ}C$, COH Type the Max. Approximately $100^{\circ}C$ ~ Min. Approximately $86^{\circ}C$ temperature stability was confirmed that, COB Type COH Type, compared to approximately $10^{\circ}C$ temperature was higher.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.50-57
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• 2024

Recently, applying a machine learning to surrogate modeling for rapid optimization of complex designs have been widely researched. Once trained, the machine learning surrogate model can predict similar outputs to Finite Element Analysis (FEA) simulations but require significantly less computing resources. In addition, combined with optimization methodologies, it can identify optimal design variable with less time requirement compared to iterative simulation. This study proposes a Deep Neural Network (DNN) model with Bayesian Optimization (BO) approach for efficiently searching the optimal design variables to minimize the warpage of electronic package. The DNN model was trained by using design variable-warpage dataset from FEA simulation, and the Bayesian optimization was applied to find the optimal design variables which minimizing the warpage. The suggested DNN + BO model shows over 99% consistency compared to actual simulation results, while only require 15 second to identify optimal design variable, which reducing the optimization time by more than 57% compared to FEA simulation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.609-610
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• 2008

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.79-83
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• 2012

LTCC (Low temperature co-fired ceramic) package have been paid much attention due its good reliability, miniaturization, and application of silver paste with complex wiring and printing. Therefore, LTCC package has been expected to replace vulnerable plastic package in the field of high power LED device. Currently, LTCC ceramic package is mainly made up of aluminum oxide powder. In this study, zinc oxide powder is added or replaced for the fabrication of LTCC ceramic body. By adding small amount of ZnO, thermal conductivity of the LTCC ceramic body could be remarkably increased by 25% leading to the extension of LED life time. The LTCC package structure with composition including ZnO has an increased thermal flux by 56% as a result of ANSYS simulation. Actually, the fabricated LED package with the addition of ZnO exhibits a decreased thermal resistivity by 14.9%.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.