• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.183-190
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• 1997

We present competition protocols to speed up the execution of sequential programs on a network of shared workstations in the background by exploiting their wasted computing capacity, without interfering with processes of workstation owners. In order to argue that competition protocols are preferable to migration protocols in this situation, we derive the closed form solutions for the speedup of competition protocols and migration protocols, and simulate both of protocols under comparable overhead assumptions. Based on our analytic results and simulation results, we show that competitive execution is superior to process migration, and that competitive execution can finish sequential programs significantly faster than noncompetitive execution, especially when the foreground load is sufficiently high.

• 한국태양에너지학회 논문집
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• 제33권3호
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• pp.1-8
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• 2013

In order to identify positive or negative effect of seawall on wind turbine, a wind tunnel experiment has been conducted with a 1/100 scaled-down model of Goonsan wind farm which is located in West coast along seawall. Wind speedup due to the slope of seawall contributed to about 3% increment of area-averaged wind speed on rotor-plane of a wind turbine which is anticipated to augment wind power generation. From the turbulence measurement and flow visualization, it was confirmed that there would be no negative effect due to flow separation because its influence is confined below wind turbine blades' sweeping height.

• Wind and Structures
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• 제19권2호
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• pp.219-232
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• 2014

The characteristics of turbulent boundary layers over hilly terrain depend strongly on the hill slope and upstream condition, especially inflow turbulence. Numerical simulations are carried out to investigate the neutrally stratified turbulent boundary layer over two-dimensional hills. Two kinds of hill shape, a steep one with stable separation and a low one without stable separation, two kinds of inflow condition, laminar turbulent, are considered. An auxiliary simulation, based on the local differential quadrature method and recycling technique, is performed to simulate the inflow turbulence be imposed at inlet boundary of the turbulent inflow, which preserves very well in the computational domain. A large separation bubble is established on the leeside of the steep hill with laminar inflow, while reattachment point moves upstream under turbulent inflow condition. There is stable separation on the side of low hill with laminar inflow, whilw not turbulent inflow. Besides increase of turbulence intensity, inflow can efficiently enhance the speedup around hills. So in practice, it is unreasonable to study wind flow over hilly terrain without considering inflow turbulence.

• 전자공학회논문지D
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• 제36D권10호
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• pp.37-44
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• 1999

건식 식각 공정을 시뮬레이션하기 위하여, 플라즈마 챔버 내의 식각 이온 거동 메카니즘을 몬테카를로 수치해석 방식으로 구현하였고, 식각 이온의 거동에 의한 기판의 식각 형상을 확인하기 위하여 셀 방식의 표면 전진기를 개발하였다. 몬테카를로 수치 계산의 단점인 과다한 계산 시간을 효과적으로 감소시키기 위하여, CRAY T3E 병렬 컴퓨터와 여러대의 워크스테이션을 연결한 MPI 환경에서 몬테카를로 병렬 계산 알고리즘을 개발하였다. 본 연구에서 개발한 몬테카를로 병렬 계산 알고리즘은 95% 이상의 효율성을 보이며, 16개의 프로세서를 사용하였을 때 16의 스피드업(Speedup) 값을 얻었다. 또한 셀 방식의 병렬 연산 표면 전진기를 이용하여 토포그래피 시뮬레이션을 수행한 결과에서, 셀의 개수가 2갭만 개 일 때, 약 600Mb 이상의 메모리가 소요되므로 단일 워크스테이션 환경에서는 불가능한 계산이 본 연구에서 개발한 병렬 계산 알고리즘을 이용하였을 때 32개의 프로세서에서 15분의 계산시간이 소요되었다.

• 한국정보처리학회논문지
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• 제5권4호
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• pp.883-891
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• 1998

본 논문에서는 원소오토마타 모델의 시뮬레이션에서 SIMD형 병렬성을 이용하는 방법을 제안한다. 제안된 방법에서는 SIMD 병렬성을 이용하여 시뮬레이션에 사용되는 컴퓨터 내에 들어 있는 ALU의 이용도를 높이고 시뮬레이션 시간을 줄인다. 그래서 몇 개의 원소들을 결합하여 하나의 표준 크기의 컴퓨터 단어로 만들고 그 원소들의 상태를 동시에 변환시킨다. 제안된 시뮬레이션 방법의 성능을 보이기 위하여, 본 논문에서는 두 가지 원소오토마타 모델을 세 가지 하드웨어 환경에서 시뮬레이션 하였다. 실험결과로부터, 모든 경우에서 시뮬레이션 속도가 매우 크게 향상되었다. 특히 최상의 경우에는 제안된 시뮬레이션 방법에 의한 속도 향상이 20배에 달하는 경우도 있었다.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1992년도 제2회 정기총회 및 추계학술 발표회 발표논문 초록
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• pp.5-5
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• 1992

The DEVS(discrete event system specification) formalism describes a discrete event system in a hierarchical, modular form. DEVSIM++ is C++ based general purpose DEVS abstract simulator which can simulate systems to be modeled by the DEVS formalism in a sequential environment. We implement P-DEVSIM++ which is a parallel version of DEVSIM++. In P-DEVSIM++, the external and internal event of models can be processed in parallel. To process in parallel, we introduce a hierarchical distributed simulation technique and some optimistic distributed simulation techniques. But in our algorithm, the rollback of a model is localized itself in contrast to the Time Warp approach. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• Journal of information and communication convergence engineering
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• 제6권1호
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• pp.59-63
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• 2008

The methods or algorithms which can accelerate simulation speed became of great importance, as the modeling and simulation methodology for discrete event systems is used in many areas such as model validation/verification and performance evaluation. This paper proposes a tool named, DEVSIF composer. The tool is made of an automated compiled simulation technology and it builds a new composed model which can be executed much fast by composing the component models together. Models are described by our new specification language DEVSIF, which is compatible with object-oriented language and supports representation of a hierarchical model structure. Experimental results demonstrates that DEVSIF composer enhances the simulation speed of a transformed DEVS model 5 times faster than that of the original ones in average.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권1호
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• 한국시뮬레이션학회논문지
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• 제1권1호
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• pp.64-76
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• 1992

The DEVS(discrete event system specificaition) formalism specifies a discrete event system in a hierarchical, modular form. DEVSIM++ is a C++based general purpose DEVS abstract simulator which can simulate systems modeled by the DEVS formalism in a sequential environment. This paper describes P-DEVSIM++which is a parallel version of DEVSIM++ . In P-DEVSIM++, the external and internal event of DEVS models can by processed in parallel. For such processing, we propose a parallel, distributed optimistic simulation algorithm based on the Time Warp approach. However, the proposed algorithm localizes the rollback of a model within itself, not possible in the standard Time Warp approach. An advantage of such localization is that the simulation time may be reduced. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• ETRI Journal
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• 제43권3호
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• pp.483-510
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• 2021

In computational biology, desired patterns are searched in large text databases, and an exact match is preferable. Classical benchmark algorithms obtain competent solutions for pattern matching in O (N) time, whereas quantum algorithm design is based on Grover's method, which completes the search in $O(\sqrt{N})$ time. This paper briefly explains existing quantum algorithms and defines their processing limitations. Our initial work overcomes existing algorithmic constraints by proposing the quantum-based combined exact (QBCE) algorithm for the pattern-matching problem to process exact patterns. Next, quantum random access memory (QRAM) processing is discussed, and based on it, we propose the QRAM processing-based exact (QPBE) pattern-matching algorithm. We show that to find all t occurrences of a pattern, the best case time complexities of the QBCE and QPBE algorithms are $O(\sqrt{t})$ and $O(\sqrt{N})$, and the exceptional worst case is bounded by O (t) and O (N). Thus, the proposed quantum algorithms achieve computational speedup. Our work is proved mathematically and validated with simulation, and complexity analysis demonstrates that our quantum algorithms are better than existing pattern-matching methods.