• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.412-416
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• 2018

Most series arcs lead to electrical fires that cannot be interrupted by circuit breakers, because the arc's current is outside the breaker's operating range. In this paper, experiments were conducted on the detection and identification of series arcs to prevent electrical fires. Plugs and outlets specified in KS C 8305 were deteriorated to replicate arc faults commonly found in fields. The characteristics of series arcs resulting from various types of loose connections were determined by analyzing the frequency spectra and phase distributions of detected arc pulses. The results showed that the simulated arc defects used in this study were more similar to actual arc phenomena than the existing arc generator specified in UL 1699. In addition, loose connections, such as wire-wire, terminal-wire, and outlet-plug, can be identified by phases of $0^{\circ}$, $180^{\circ}$ and $360^{\circ}$, respectively. These phases can be detected by a band pass filter with a frequency range of 5~10 MHz, which can be used as the trip signal for circuit breakers.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.25-32
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.19 no.3
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• pp.97-103
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• 2018

This paper addresses an improved naval combat UPS(Uninterruptable Power Supply) system under abnormal transients. Previously, thermistor and varistor elements were used to cope with transient overvoltage and overcurrent, however the UPS was frequently unavailable because it was vulnerable to abnormal transient voltage generated during system operation. In order to overcome this problem and protect UPS system, this paper proposes an input power cut-off circuit that detects the initial input power and abnormal transient voltage generated during operation, improvement of power control sequence, and a method to prevent malfunction of an inverter and CPU. The UPS system implementing the proposed method was simulated by input power variable test using programmable AC/DC generator, and finally validated its reliability and stability through field tests by mounting on multifunctional console of naval combat system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Journal of the Korean Society for Nondestructive Testing
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• v.18 no.6
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• pp.464-476
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• 1998

Determination of location, shape and size of a flaw from its eddy current testing signal is one of the fundamental issues in eddy current nondestructive evaluation of steam generator tubes. Here, we propose an approach to this problem; an inversion of eddy current flaw signal using neural networks trained by finite element model-based synthetic signatures. Total 216 eddy current signals from four different types of axisymmetric flaws in tubes are generated by finite element models of which the accuracy is experimentally validated. From each simulated signature, total 24 eddy current features are extracted and among them 13 features are finally selected for flaw characterization. Based on these features, probabilistic neural networks discriminate flaws into four different types according to the location and the shape, and successively back propagation neural networks determine the size parameters of the discriminated flaw.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.2
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• pp.90-98
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• 2006

Signals captured from a Combo calibration standard tube paly a crucial role in the evaluation of motorized rotating pancake coil (MRPC) probe signals from steam generator (SG) tubes in nuclear power plants (NPPs). Therefore, the Combo tube signals should be consistent and accurate. However, MRPC probe signals are very easily affected by various factors around the tubes so that they can be distorted in their amplitudes and phase angles which are the values specifically used in the evaluation. To overcome this problem, in this study, we explored possibility of simulation to be used as a practical calibration tool far the evaluation of real field signals. For this purpose, we investigated the characteristics of a MRPC probe and a Combo tube. And then using commercial software (VIC-3D) we simulated a set of calibration signals and compared to the experimental signals. From this comparison, we verified the accuracy of the simulated signals. Finally, we evaluated two defects using the simulated Combo tube signals, and the results were compared with those obtained using the actual field calibration signals.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.121-127
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• 2020

The small tracking radar targets the target in a real-time, fast-moving, fast-moving target against aircraft with a large RCS that is maneuvering at low speed and a small RCS aircraft maneuvering at high speed (fighters, drones, helicopters, etc.) It is a pulsed radar that detects and tracks. Performing a performance test on a tracking radar in a real environment is expensive, and it is difficult to quantitatively measure performance in a real environment. Describes the composition of the laboratory environment's comprehensive performance test facility and the main requirements and implementation of each configuration.Anechoic chambers to simulate the room environment, simulation target generator to simulate the signal of the room target, target It is composed of a horn antenna driving device to simulate the movement of a vehicle and a Flight Motion Simulatior (FMS) to simulate the flight environment of a tracking radar, and each design and implementation has been described.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.