• The Korean Journal of Pain
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• v.35 no.4
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• pp.403-412
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• 2022

Background: Most pain management techniques for challenging procedures are still performed under the guidance of the C-arm fluoroscope although it is sometimes difficult for even experienced clinicians to understand the modified three-dimensional anatomy as a two-dimensional X-ray image. To overcome these difficulties, the development of a virtual simulator may be helpful. Therefore, in this study, the authors developed a virtual simulator and presented its clinical application cases. Methods: We developed a computer program to simulate the actual environment of the procedure. Computed tomography (CT) Digital Imaging and Communications in Medicine (DICOM) data were used for the simulations. Virtual needle placement was simulated at the most appropriate position for a successful block. Using a virtual C-arm, the authors searched for the position of the C-arm at which the needle was visualized as a point. The positional relationships between the anatomy of the patient and the needle were identified. Results: For the simulations, the CT DICOM data of patients who visited the outpatient clinic was used. When the patients revisited the clinic, images similar to the simulated images were obtained by manipulating the C-arm. Transforaminal epidural injection, which was difficult to perform due to severe spinal deformity, and the challenging procedures of the superior hypogastric plexus block and Gasserian ganglion block, were successfully performed with the help of the simulation. Conclusions: We created a pre-procedural virtual simulation and demonstrated its successful application in patients who are expected to undergo challenging procedures.

• Journal of The Korean Association of Information Education
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• v.15 no.4
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• pp.533-542
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• 2011

In this paper, we have selected traveling algorithms of Line-Tracer as the focused learning elements with the PBL-based programming instruction method. Line-Tracer traveling algorithm programming has been simulated using the Scratch EPL. Development of robot web courseware such as Line-Tracer can create an effective educational environment and also provide solutions for lack of environmental conditions, such as time or spatial factor restrictions and excessive expense issues; these are major obstacles to developing robot programming education. Finally, we analyzed the effects on growth of student's logical thinking and problem solving abilities by demonstrating the Scratch application courseware to the field of elementary education.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.82-92
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• 2001

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

• Proceedings of the Korean Geotechical Society Conference
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• 2002.03a
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• pp.445-452
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• 2002

In the field of civil and geotechnical engineering, students conduct a variety of soil tests to fulfill undergraduate soil mechanics course requirement. There is a range of problems in soil laboratory instruction, such as, some students not getting hands on experience of conducting tests because of inadequate number of apparatus, time constraints and inability in exciting students to seriously conduit the experiments, However when these laboratory soil tests are simulated with multimedia interaction ann visualization techniques, the students conceptual understanding of soil mechanics is enhanced. The simulation program for website teaching is a computer based instructional package intended to complement, and potentially replace, some physical testing in a real soil laboratory. The overall aim of this project is to develop an experimental simulation program toward active learning and development of critical thinking skills, including data interpretation, understanding of the precesses and influential factors, and problem solving. Therefore enable students to access website to team experimental procedure at any time or place.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of The Korean Association of Information Education
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• v.24 no.3
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• pp.243-254
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• 2020

In order to cultivate AI(artificial intelligence) manpower, major countries are making efforts to apply AI education from elementary school. In order to introduce AI education in elementary school, it is necessary to have a curriculum and educational content for elementary school level. This study developed educational contents to experience the principle of AI learning at the unplugged level for the purpose of AI education for elementary school students. The educational content developed was selected as an AI that evaluates the emotion of sentences. In addition, to solve the problem, data attributes were derived and collected, and the process of AI learning was simulated to solve the problem. As a result of the study, the attitude of elementary school students to AI increased post than before. In addition, the task performance rate was averaged at 85%, showing that the proposed AI education content has educational significance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.135-141
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• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.