• Title/Summary/Keyword: Simulated Instruction

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Prediction of Flow Pattern inside a Power Condenser by Computer Modelling (전산모델에 의한 응축기내에서의 기체유동현상의 예측)

  • Seoul, Kwang Won;Lee, Sang Yong
    • The Magazine of the Society of Air-Conditioning and Refrigerating Engineers of Korea
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    • v.17 no.3
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    • pp.238-248
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    • 1988
  • The flow pattern inside the power condenser is generally known to be very complicated due to the phase change and turbulence effects as well as the effect of condenser geometry. In the present study, the flow pattern inside the power condenser was numerically simulated with a personal computer. The widely known CHAMPION 2/E/FIX(Concentration, Heat and Momentum Program Instruction Outfit, 2D/Elliptic/Fixed grid) computer code was modified for this purpose. The flow was asssumed to be two-dimensional and steady-state, and the tube bank was considered to be homogeneous porous medium. Simple turbulent diffusion coefficients based on the appropriate experiments were obtained for the computation. Through this analytical approach, the flow pattern could be predicted fairly well. The computational results also show that the location of the air vent plays an important key role in determining the efficiency of the condenser.

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Design and Simulation of an RSFQ 1-bit ALU (RSFQ 1-bit ALU의 디자인과 시뮬레이션)

  • 김진영;백승헌;강준희
    • Progress in Superconductivity
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    • v.5 no.1
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    • pp.21-25
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    • 2003
  • We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were +/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

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Output encoding methods for the design of insturction decoder (명령어 해독기 설계를 위한 출력 부호화 방법)

  • 김한흥;황승호;경종민
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.132-140
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    • 1994
  • In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

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A DSP Architecture for High-Speed FFT in OFDM Systems

  • Lee, Jae-Sung;Lee, Jeong-Hoo;SunWoo, Myung-H.;Moh, Sang-Man;Oh, Seong-Keun
    • ETRI Journal
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    • v.24 no.5
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    • pp.391-397
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    • 2002
  • This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

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Delay Test for Boundary-Scan based Architectures (경계면 스캔 기저 구조를 위한 지연시험)

  • 강병욱;안광선
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.6
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    • pp.199-208
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    • 1994
  • This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

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Architecture design and FPGA implementation of a system control unit for a multiprocessor chip (다중 프로세서 칩을 위한 시스템 제어 장치의 구조설계 및 FPGA 구현)

  • 박성모;정갑천
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.12
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    • pp.9-19
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    • 1997
  • This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

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Implementation of a Real-time SIFT Pitch Detector (실시간 SIFT 기본주파수 검출기의 구현)

  • Lee, Jong Seok;Lee, Sang Uk
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.1
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    • pp.101-113
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    • 1986
  • In this paper, a real-time pitch detector LPC vocoder as implemented on a high speed digital signal processor, NEC 7720, is described. The pitch detector was based mainly on the SIFT algorithm. The SIFT pitch detector consists primarily of a digital low pass filter, inverse filter, computation of autocorrelation, a peak picker, interpolation, V/UV defcision and a final pitch smoother. In our approach, modification, mainly on the V/UV decision and a final pitch smoother, was made to estimate more accurate pitches. An 16-bit fixed-point aithmatic was employed for all necessary computation and the simulated results were compared with the eye detected pitches obtained from real speech data. The pitch detector occupies 98.8% of the instruction ROM, 37% of the data ROM, and 94% of internal RAM and takes 15.2ms to estimate a pitch when an analysis frame is consisted of 128 sampled speech data. It is observed that the tested results were well agreed with the computer simulation results.

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The Direction for Development of Domestic Initial Response System for Chemical Terrorism (국내 화학테러 초기대응체제의 발전방향 (한·미 화학테러 초기대응체제 비교를 중심으로))

  • Eun, Chong-hwa
    • Journal of the Society of Disaster Information
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    • v.5 no.2
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    • pp.50-73
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    • 2009
  • This paper is about the establishment of "Initial Response System." Initial response system is most important and should be treated urgently among all preparations for chemical terrorism. The objects of Initial response system are to protect civilians and the first responder who are exposed directly to chemical terrorism. Therefore, this paper suggests two main issues about Initial response system. One is to prepare immediate and exact information service system which assures the safety and survival of exposed people. The other is to build Scene Response System integrated with Command-Control Procedure for early finished situation. Compared to United States, overcoming the Chemical Terrorism requires to improve the contents of two categories: Counter Citizen Response part and Initial Scene Response part. For Counter citizen response part' s sake, the web-sites of Response leader agencies for searching information about chemical terrorism should be modified specifically. These web-sites have to be re-organized in detail. The existing Information service system which has been vaguely informed as "CBRNE Accident" needs to be divided as "CBRNE Accident" and "WMD terrorism." Further, each of them should be specialized in "Chemical', "Biological", and "Radiological" categories. There is a need to rearrange current Emergency Instruction for civilians against chemical terrorism in feasible way. At the same time, it should be applied consistently to all organizations through agreement between experts and related-organizations. For Initial Scene Response part's sake, "Initial scene response procedure (SOP)" and "Operational conception" should be produced through Simulated Exercises and workshops of all organizations related with initial response. These organizations have to cooperate with Ministry of Environment which is the main leader Agency as the center. Next, there is a need to develop a technology and Scene Response Equipments, and to standardize the response equipments which consider the capability of First Responders for chemical terrorism. Especially, improving capability of equipments is required to overcome the vulnerability of Scene Response Equipments.

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Development of selectable observation point test architecture in the Boundry Scan (경계면스캔에서의 선택가능한 관측점 시험구조의 개발)

  • Lee, Chang-Hee;Jhang, Young-Sig
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.4
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    • pp.87-95
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    • 2008
  • In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

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A Study on Physical Activities in the Teachers' Guidance Manual for the Nuri Curriculum of Four-Year-old Children -Focusing on Pre-service Early-childhood Teachers' Simulated Instruction - (예비유아교사의 모의수업을 통해 본 「4세 누리과정 교사용 지도서 신체활동」 분석)

  • Hong, Kil Hoe;Youn, Hea Ja
    • Korean Journal of Childcare and Education
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    • v.11 no.2
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    • pp.177-200
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    • 2015
  • The purpose of this study is to analyze physical activities in 'Teachers' Guidance Books for the Nuri Curriculum of 4-year-old children' through simulated instruction of pre-service teachers and, through this, to help them better perform physical activities in their field education for early-aged. The subjects of the study were 30 sophomore students in the early-aged children's Education Department in their 2ndsemester of K University located in Gyeonggi-province. For the analysis of physical activities in 'Teachers' Guidance Books for Nuri Curriculum of 4-year-old children', a qualitative study was conducted and data were collected through informal interviews, reflective journals of pre-service teachers and 30 sessions of education assessment sports. The results of the analysis on the physical activities in 'Teachers' Guidance Books for Nuri Curriculum of 4-year-old children' are as follows; first, preliminary teachers of early-aged children understood the major goal of physical activities in 'Teachers' Guidance Books for Nuri Curriculum of 4-year-old children' as 'expressing.' Second, the teachers thought careful analysis is required on media such as 'video, illustration books, sounds, picture materials' presented together with physical activities in 'Teachers' Guidance Books for Nuri Curriculum of 4-year-old children.' Third, teachers pointed out 'activities that were difficult to understand for pre-service early childhood teachers' and 'improperly presented activities different from the title' as errors and problems in the performance of the Nuri Curriculum. Fourth, as for 'points to make improvement on', pre-service early childhood teachers' requested basic physical activities before the actual activities, the provision of proper actual materials, the necessity of active demonstrations of teachers and making a regulation for the situation of physical activities by early-aged children and teachers together. The results of the study illustrate that deep contemplation and judgment is required of the teachers before conducting physical activities of the Nuri Curriculum.