• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.241-241
• /
• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
• /
• pp.263-267
• /
• 2002

We are standing at the beginning of the industrialization of flexible thin-film transistor backplanes. An important group of candidates is based on silicon thin films made on metal or plastic foils. The main features of amorphous, nanocrystalline and microcrystalline silicon films for TFTs are summarized, and their compatibility with foil substrate materials is discussed.

• 한국광학회:학술대회논문집
• /
• 한국광학회 2003년도 제14회 정기총회 및 03년 동계학술발표회
• /
• pp.322-323
• /
• 2003

Silicon substrate was fabricated by bulk silicon micromachining and it's structure is based on a proof mass suspended by two beam. To monitor the acceleration, dynamic excitation of accelerometer was performed using a shaker. The attached FFPI and suspension beam are bent because support beam move with variation of the proof mass. Thus phase difference detected by the acceleration change. So we can know that resonance frequency of fabricated accelerometer is about 557 Hz and dynamic range was measured from 0 g to 2 g.

• Bulletin of the Korean Chemical Society
• /
• 제34권4호
• /
• pp.1296-1299
• /
• 2013

• 한국결정성장학회지
• /
• 제5권1호
• /
• pp.37-43
• /
• 1995

실리콘의 용액성장을 위해서는 우선 적절한 용매의 선택이 선행되어야 한다. 이 논문에서는 최소한의 실리콘을 (1 atomic%) 고용할 수 있는 온도를 여러 용매를 대상으로 계산하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
• /
• pp.497-502
• /
• 1998

To understand the effect of surface roughness on silicon wafer bonding, a continuum mechanical model is presented. This model is based on Obreimoff's experiment and the contact theory of rough surfaces. The surface energy of silicon was calculated to be much reduced than the theoretical value. Problems are discussed concerning surface film effects and the assumption of constant asperity radius and statistical distribution function.

• 공업화학
• /
• 제16권5호
• /
• pp.614-619
• /
• 2005

폴리올, 실리콘 수지, 변성 실리콘 수지 등을 유화제로 유화시켜 수용성 소포제를 제조하였다. 제조한 소포제에 대하여 소포성, 상분리 시간, 점도 등을 측정하였다. PPG 혼합물의 상분리 시간은 PPG 400>PPG 3000>PPG 1000이었다. PPG 1000을 혼합하였을 때는 다른 것에 비하여 뛰어난 소포성을 나타내었다. 실리콘 수지 혼합물의 상분리 시간은 TSF-451-350>TSF-451-200>TSF-451-50이었다. TSF-451-50을 혼합하였을 때는 상용성 부족으로 혼합물의 부피가 증가되었다. 고분자량의 실리콘 수지를 사용할수록 소포성은 좋지 않았다. 변성 실리콘 수지는 물에 잘 분산되었지만 폴리올에 대한 상용성은 좋지 않았다. 유화제에 대한 소포성은 SPAN 20>SPAN 60>SPAN 80의 순이었다. SPAN 80은 실리콘 수지에 대하여 혼합성이 좋지 않았지만 YAS 6406이나 PPG 1000에 대해서는 좋은 혼합성을 나타내었다.

• 센서학회지
• /
• 제20권3호
• /
• pp.213-218
• /
• 2011

The load cell is a force sensor and a transducer that is used to convert a physical force into a electrical signal for weighing equipment. Most conventional load cells are widely used a metal foil strain gauge for sensing element when force being applied spring element in order to converts the deformation to electrical signals. The sensitivity of a load cell is limited by its low gauge factor, hysteresis and creep. But silicon-based sensors perform with higher reliability. This paper presents the basic design and development of the silicon type load cell with an SUS630 diaphragm. The load cell consists of two parts the silicon strain gauge and the SUS630 structure with diaphragm. Structure analysis of load cell was researched by theory to optimize the load cell diaphragm design and to determine the position of peizoresistors on a silicon strain gauge. The piezo-resistors are integrated in the four points of silicon strain gauge processed by ion implantation. The thickness of the silicon strain gauge was polished by CMP under 100 ${\mu}M$. The 10 mm diameter SUS630 diaphragm was designed for loads up to 10 kg with 300 ${\mu}M$ of diaphragm thickness. The load cell was successfully tested, the variation of ${\Delta}$R(%) of four points on the silicon strain gauge is good linearity properties and sensitivity.

• 한국재료학회지
• /
• 제27권5호
• /
• pp.263-269
• /
• 2017

Fe-Si-Cr ferroalloy is predominantly produced by carbothermic reduction. In this study, silicothermic and carbothermic mixed reduction of chromite ore to produce Fe-Si-Cr alloy is suggested. As reductants, silicon and silicon carbide are evaluated by thermochemical calculations, which prove that silicon carbide can be applied as a raw material. Considering the critical temperature of the change from the carbide to the metallic form of chromium, thereduction experiments were carried out. In these high temperature reactions, silicon and silicon carbide act as effective reductants to produce Fe-Si-Cr ferroalloy. However, at temperatures lower than the critical temperature, silicon carbide shows a slow reaction rate for reducing chromite ore. For the proper implementation of a commercial process that uses silicon carbide reductants, the operation temperature should be kept above the critical temperature. Using equilibrium calculations for chromite ore reduction with silicon and silicon carbide, the compositions of reacted metal and slag were successfully predicted. Therefore, the mass balance of the silicothermic and carbothermic mixed reduction of chromite ore can be proposed based on the calculations and the experimental results.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.413-413
• /
• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.