• Transactions on Electrical and Electronic Materials
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• 제14권1호
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• pp.16-19
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• 2013

Frequency filters with various filtering wavelengths were used in the photoelectric characterization of hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) and the experimental results were described and analyzed in terms of the photon energy spectral characteristics calculated from the integration of the photon energy and the spectral intensity of transmitted backlight through the filters at each wavelength. From the comparison of the photocurrents and the calculated photon energy spectrums for the filtered ranges of wavelength, it was possible to conclude that the photocurrents are closely related to the photon energy spectrums of the backlight.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.257-260
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• 2010

Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.332-333
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• 2008

DC magnetron sputtering was used to deposit p-type polycrystalline silicon on n-type Si(100) wafer. The influence of film microstructure properties on deposition parameters (DC power, substrate temperature, pressure) was investigated. The substrate temperature and pressure have the important influence on depositing the poly-Si thin films. Smooth ploy-Si films were obtained in (331) orientation and the average grain sizes are ranged in 25-30nm. The grain sizes of films deposited at low pressure of 10mTorr are a little larger than those deposited at high pressure of 15mTorr.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1050-1053
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• 2002

In this paper, Amorphous silicon on glass substrate was recrystallized to poly-crystalline silicon by solid phase crystallization (SPC) technology. The active region of thin film transistor (TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain (LDD) structure was measured and analyzed. As a results, analyzed TFTs reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.185-188
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• 2002

In this paper, Amorphous silicon on glass substrate was recrytallized to poly-crystalline silicon by solid phase crystallization(SPC) technology The active region of thin film transistor(TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain(LDD) structure was measured and analyzed. As a results, analyzed TFT's reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations

• 한국주조공학회지
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• 제32권5호
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• pp.211-218
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• 2012

The effects of thickness, silicon and manganese contents on the mechanical properties of 3.3 wt%C-0.1 wt%S thin-section gray cast iron plates were investigated. The eutectic cell counts and volume fraction of pearlite in the matrix decreased with increased thickness and therefore the strength and hardness decreased with it. Even though the eutectic cell count increased with increased silicon content, the volume fraction of pearlite decreased and the strength and hardness decreased with it. The pearlite was refined more with increased manganese content and therefore the strength and hardness increased with it.

• 한국재료학회지
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• 제12권4호
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• pp.240-247
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• 2002

Tin oxide thin films doped with silicon as anodes for lithium secondary battery were fabricated by R.F. magnetron sputtering technique. The electrochemical results showed that the irreversible capacity was reduced during the first discharge/charge cycle, because the audition of silicon decreased the oxidic state of Tin. Capacity was increased with the increase of substrate temperature, however decreased with the increase of RTA temperatures. The reversible capacity of thin films fabricated under the substrate temperature of $300^{\circ}C$ and the Ar:$O_2$ratio of 7:3 was 700mA/g.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.112-115
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• 2011

To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.

• 한국세라믹학회지
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• 제35권6호
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• 대한전기학회논문지
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• 제45권4호
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• pp.568-573
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• 1996

The amorphous silicon films deposited by low pressure chemical vapor deposition are crystallized by the various annealing techniques including low-temperature furnace annealing and two-step annealing. Two-step annealing is the combination of furnace annealing at 600 [.deg. C] for 24 h and the sequential furnace annealing at 950 [.deg. C] 1h or the excimer laser annealing. It s found that two-step annealings reduce the in-grain defects significantly without changing the grain boundary structure. The performance of the poly-Si thin film transistors (TFTs) produced by employing the tow-step annealing has been improved significantly compared with those of one-step annealing. (author). 13 refs., 6 figs., 1 tab.