• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.116-116
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• 2011

오늘날 표시장치는 경량, 고밀도, 고해상도 대면적화의 요구에 의해 TFT-LCD의 발전이 이루어졌다. TFT에는 반도체 재료로서, Poly-Si을 사용하는 Poly-Si TFT와 a-Si:H를 이용하는 a-Si;H TFT가 있는데 a-Si는 $350^{\circ}C$ 이하의 저온으로 제작이 가능하여 많이 사용되고 있다. 이러한 방향에 맞추어 bottom gate 구조의 a-Si TFT 실험을 진행하였다. P-type silicon substrate ($0.01{\sim}0.02{\Omega}-cm$)에 gate insulator 층인 SiNx (SiH4 : NH3 = 6:60)를 200nm 증착하였다. 그리고 그 위에 active layer 층인 a-Si (SiH4 : H2 : He =2.6 : 10 : 100)을 다른 RF power를 적용하여 100 nm 증착하였다. 그 위에 Source와 Drain 층은 Al 120 nm를 evaporator로 증착하였다. active layer, gate insulator 층은 ICP-CVD 장비를 이용하여 증착하였으며, 공정온도는 $300^{\circ}C$ 로 고정하였다. active layer층 증착시 RF power는 100W, 300W, 500W, 600W로 가변하였고, width/length는 100 um/8um로 고정하였다. 증착한 a-Si layer층을 Raman spectroscope, SEM 측정 하였으며, TFT 제작 후, VG-ID, VD-ID 측정을 통해 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio를 비교해 보았다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.299-299
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• 2011

A dipolar interlayer can cause dramatic changes in the device characteristics of organic field-effect transistors (OFETs) or photovoltaics. A shift in the threshold voltage, for example, has been observed in an OFET where the organic semiconductor active layer is deposited on SiO2 modified with a dipolar monolayer. Dipolar molecules can similarly be used to change the current-voltage characteristics of organic-inorganic heterojunctions. We have conducted a series of experiments in which different molecular linkages are placed between a pentacene thin film and a silicon substrate. Interface modifications with different linkages allow us to predict and examine the nature of tunneling through pentacene on modified Si surfaces with different dipole moment. The molecular-scale structure and the tunneling properties of pentacene thin films on modified Si (001) with nitrobenzene and styrene were examined using scanning tunneling spectroscopy. Electronic interfaces using organic surface dipoles can be used to control the band lineups of a semiconductor at organic/inorganic interfaces. Our results can provide insights into the charge transport characteristics of organic thin films at electronic interfaces.

• 한국재료학회지
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• 제13권9호
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• pp.606-612
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• 2003

Surface and mechanical properties of thin films with submicron thickness was characterized by nanoindentation with Berkovich and Vickers tips, and scanning probe microscopy. Nanoindention was made in a depth range of 15 to 200 nm from the surface by applying tiny force in a range from 150 to $9,000 \mu$N. Stiffness, contact area, hardness, and elastic modulus were determined from the force-displacement curve obtained. Reliability was first tested by using fused quartz, a standard sample. Elastic modulus and hardness values of fused quartz measured were the same as those reported in the literature within two percent of error. Mechanical properties of ITO thin film were characterized in a depth range of 15∼200nm. As indentation depth increased, elastic modulus and hardness decreased by substrate effect. Ion beam deposited DLC thin films were indented in a depth range of 40∼50 nm. The results showed that the DLC thin film using benzene and bias voltage 0∼-50 V has elastic modulus and hardness value of 132 and 18 GPa respectively. Pure DLC thin films showed roughnesses lower than 0.25 nm, but silicon-added DLC thin films showed much higher roughness values, and the wavy surface morphology.

• 한국재료학회지
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• 제25권11호
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• pp.622-629
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• 2015

Cu circuits were successfully fabricated on flexible PET(polyethylene terephthalate) substrates using wettability difference and electroless plating without an etching process. The wettability of Cu plating solution on PET was controlled by oxygen plasma treatment and $SiO_x$-DLC(silicon oxide containing diamond like carbon) coating by HMDSO(hexamethyldisiloxane) plasma. With an increase of the height of the nanostructures on the PET surface with the oxygen plasma treatment time, the wettability difference between the hydrophilicity and hydrophobicity increased, which allowed the etchless formation of a Cu pattern with high peel strength by selective Cu plating. When the height of the nanostructure was more than 1400 nm (60 min oxygen plasma treatment), the reduction of the critical impalement pressure with the decreasing density of the nanostructure caused the precipitation of copper in the hydrophobic region.

• Journal of Information Display
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• 제3권2호
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• pp.1-5
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• 2002

A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on-chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the row, column and pixel driving parts. 256 gray scales were implemented using pulse amplitude modulation method. The 2-transistor driving scheme was adopted for the pixel driving part. The layout was carried out considering the compatibility with the standard CMOS process. Judging from the layout of the driving circuit, it turns that it is possible to implement a high-resolution display about 400 ppi resolution. Through the HSPICE simulation, it was verified that this circuit is capable of driving a VGA signal mode display and implementing 256 gray levels.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.69-70
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• 2000

There are currently considerable interest in the applications of conjugated polymers, oligomers, and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field-effect transistors and light-emitting diodes. In this study, pentacene thin-film transistors (TFTs) were fabricated on glass substrate. Aluminums were used for gate electrodes. Silicon dioxide was deposited as a gate insulator by PECVD and patterned by reactive ion etching (R.I.E). Gold was used for the electrodes of source and drain. The active semiconductor pentacene layer was thermally evaporated in vacuum at a pressure of about $10^{-8}$ Torr and a deposition rate $0.3{\AA}/s$. The fabricated devices exhibited the field-effect mobility as large as 0.07 $cm^2/V.s$ and on/off current ratio as larger than $10^7$.

• 한국전자파학회논문지
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• 제13권10호
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• pp.1048-1053
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• 2002

본 논문에서는 2 GHz 대역의 격자형 및 평형 구조를 가지는 박막공진 여파기를 설계, 제작하고 분석하였다. 단위공진자의 앞전물질은 AIN를 사용하였고, 전극도체로는 백금을 사용하였으며, 하부도체와 기판사이에 공기층이 있는 구조로 제작되었다. 제작된 여파기들은 크기가 작고 낮은 삽입손실과 격자형의 경우 약 15 dB, 평형 구조의 경우 약 30 dB 정도의 선택도를 가진다. 격자형 및 평형 구조는 사다리형 구조와 같이 실리콘 기판위에 제작되었으며, 사다리형 구조에 비해 넓은 대역폭을 가지며 평형구조의 경우 이외의 튜닝과정 없이 RF 여파기로 사용될 수 있다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권8호
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• pp.451-454
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• 2000

We have grown vertically aligned carbon nanotubes in a large area of Co-Ni codeposited Si substrates by the thermal CVD usign $C_2H_2$ gas. Since the discovery of carbon nanotubes, growth of carbon nanotubes has been achieved by several methods such as laser vaporization, arc discharge, and pyrolysis. In particular, growth of vertically aligned nanotubes is important to flat panel display applications. Recently, vertically aligned carbon nanotubes have been grown on glass by PECVD. Aligned carbon nanotubes can be also grown on mesoporous silica and Fe patterned porous silicon using CVD. In this paper, we demonstrate that carbon nanotubes can be vertically aligned on catalyzed Si substrate when the domain density of catalytic particles reaches a certain value. We suggest that steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically and each nonotubes are grown in bundle.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.291-294
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• 1996

We present the experimental results of high quality factor (Q) inductors fabricated on high-resistivity silicon wafer using standard CMOS process without any modificatons such as thick gold layer or multilayer interconnection. This demonstrates the possibility of building high Q inductors using lower cost technologies, compared with previous results using complicated process. The comparative analysis is carried out to find the optimized inductor shape for the maximum performance by varying the thickness of metal and number of turns with rectangular shape.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.447-450
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• 2003

This paper presents a process optimization of antireflection (AR) coating on crystalline Si solar cells. Theoretical and experimental investigations were performed on a double-layer AR (DLAR) coating of MgF$_2$/CeO$_2$. We investigated CeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. RF sputter grown CeO$_2$ film showed strong dependence on a deposition temperature. The CeO$_2$ deposited at 40$0^{\circ}C$ exhibited a strong (111) preferred orientation and the lowest surface roughness of 6.87 $\AA$. Refractive index of MgF$_2$ film was measured as 1.386 for the most of growth temperature. An optimized DLAR coating showed a reflectance as low as 2.04% in the wavelengths ranged from 0.4${\mu}{\textrm}{m}$ to 1.1${\mu}{\textrm}{m}$. We achieved the efficiencies of solar cells greater than 15% with 3.12% improvement with DLAR coatings. Further details on MgF$_2$, CeO$_2$ films, and cell fabrication parameters are presented in this paper.