• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.131-131
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• 2008

Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used a Monte-Carlo method. We studied the effect of channeling by Al implantation simulation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the Al distribution in 4H-SiC through the variation of the implantation energies and the corresponding ratio of the doses. The implantation energies controlled 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2\times10^{14}$ to $1\times10^{15}cm^{-2}$. In the simulation results, the Al ion distribution was deeper as increasing implantation energy and the doping level increased as increasing implantation doses. After the post-implantation annealing, the electrical properties of Al-implanted p-n junction diode were investigated by SILV ACO ATLAS numerical simulator.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제54권3호
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• pp.109-113
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• 2005

It has been reported that the failure phenomenon and variation of electrical characteristic due to the effect of electrostatic discharge(ESD) in silicon devices. But we had fess reports about the phenomenon due to the ESD in the compound semiconductors. So there are a lot of difficulty to the phenomenon analysis and to select the protection method of main circuits or the devices. It has not been reported that the relation between the ESD stress and GaN devices, which is remarkable to apply the operation in high temperature and high voltage due to the superior material characteristic. We studied that the characteristic variation of the AlGaN/GaN HEMT current, the leakage current, the transconductance(gm) and the failure phenomenon of device due to the ESD stress. We have applied the ESD stress by transmission line pulse(TLP) method, which is widely used in ESD stress experiments, and observed the variation of the electrical characteristic before and after applying the ESD stress. The on-current trended to increase after applying the ESD stress. The leakage current and transconductance were changed slightly. The failure point of device was mainly located in middle and edge sides of the gate, was considered the increase of temperature due to a leakage current. The GaN devices have poor thermal characteristic due to usage of the sapphire substrate, so it have been shown to easily fail at low voltage compared to the conventional GaAs devices.

• 대한전자공학회논문지SD
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• 제39권9호
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• pp.19-27
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• 2002

실리콘 기판가 교차하는 금속 선의 밑층 기하구조를 고려한 연결선로의 특성이 정교하게 고안된 패턴을 가지고 실험적으로 분석되었다. 이 작업에서, 여러 종류의 밑층 기하구조에 따른 전송선로을 위한 테스트 패턴들을 고안하였고, 신호 특성과 반응은 S-parameter 와 TDR을 통해 측정되었다. 사용된 패턴은 두 개의 알루미늄 선과 한 개의 텅스텐 선을 가지는 deep-submicron CMOS DRAM 기술을 가지고 설계되고 제작되었다. 패턴위에서 측정되 결과 분석으로부터, 라인 파라메터들 (특히 라인 커패시턴스와 저항) 과 그것들에 의한 신호 왜곡에 대한 밑층 구조에 의한 효과는 무시 할수 없음을 발견하였다. 그러한 결과는 고속 클럭과 데이터 라인 같은 글로벌 신호 선이나 패키지 리드의 스큐 발렌스의 심도있고 유용한 이해에 도움이 된다.

• 한국세라믹학회지
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• 제45권4호
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• pp.245-249
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• 2008

The SiC and ZrC are critical and essential materials in TRISO coated fuel particles since they act as protective layers against diffusion of metallic and gaseous fission products and provides mechanical strength for the fuel particle. However, SiC and ZrC have critical disadvantage that SiC loses chemical integrity by thermal dissociation at high temperature and mechanical properties of ZrC are weaker than SiC. In order to complement these problems, we made new combinations of the coating layers that the ZrC layers composed of SiC. In this study, after Silicon carbide(SiC) were chemically vapor deposited on graphite substrate, Zirconium carbide(ZrC) were deposited on SiC/graphite substrate by using Zr reaction technology with Zr sponge materials. The different morphologies of sub-deposited SiC layers were correlated with microstructure, chemical composition and mechanical properties of deposited ZrC films. Relationships between deposition pressure and microstructure of deposited ZrC films were discussed. The deposited ZrC films on SiC of faceted structure with smaller grain size has better mechanical properties than deposited ZrC on another structure due to surface growth trend and microstructure of sub-deposited layer.

• 한국전기전자재료학회논문지
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• 제11권12호
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• pp.1122-1127
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• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.190-191
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• 2006

We have investigated optical properties of Si/graded-$Si_{1-x}Ge_x$/Si heterostructures grown by reduced pressure chemical vapor deposition. Compared to standard condition using Si(100) substrate and growth temperature of $650^{\circ}C$, Si(111) resulted in low growth rate and high Ge mole fraction. Also samples grown at higher temperatures exhibited increased growth rate and reduced Ge mole fraction. The features regarding both substrate temperature and crystal orientation, representing high incorporation of silicon supplied from gas stream played as a key parameter, illustrate that reaction control were prevailed in this process growth condition. Using secondary ion mass spectroscopy and spectroscopic ellipsometry, microscopic changes in atomic components could be analyzed for Si/graded-$Si_{1-x}Ge_x$/Si heterostructures.

• 한국재료학회지
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• 제15권11호
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• pp.705-710
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• 2005

NIL (nanoimprint lithography) technique has demonstrated a high potential for wafer size definition of nanometer as well as micrometer size patterns. During the replication process by NIL, the stiction between the stamp and the polymer is one of major problems. This stiction problem is moi·e important in small sized patterns. An antistiction layer prevents this stiction ana insures a clean demolding process. In this paper, we were using a TCP (transfer coupled plasma) equipment and $C_4F_8$ as a precursor to make a Teflon-like antistiction layer. This antistiction layer was deposited on a 6 inch silicon wafer to have nanometer scale thicknesses. The thickness of deposited antistiction layer was measured by ellipsometry. To optimize the process factor such as table height (TH), substrate temperature (ST), working pressure (WP) and plasma power (PP), we were using a design of experimental (DOE) method. The table of full factorial arrays was set by the 4 factors and 2 levels. Using this table, experiments were organized to achieve 2 responses such as deposition rate and non-uniformity. It was investigated that the main effects and interaction effects between parameters. Deposition rate was in proportion to table height, working pressure and plasma power. Non-uniformity was in proportion to substrate temperature and working pressure. Using a response optimization, we were able to get the optimized deposition condition at desired deposition rate and an experimental deposition rate showed similar results.

• 접착 및 계면
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• 제19권4호
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• pp.163-166
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• 2018

이 딥펜 나노리소그라피(DPN)는 원자 힘 현미경(AFM)을 기반으로 하는 나노 및 마이크로 패턴 제조 기술이다. 다양한 잉크 물질을 AFM 탐침에 코팅하여 탐침과 기판 사이에 형성된 물 메니스커스를 통해 기판으로 전이시켜 패턴을 제조한다. 본 연구에서는, 실란 전처리된 AFM 탐침 표면에 불소 실란 잉크 용액을 코팅하고 하이드록시기로 개질된 실리콘 기판 위에 접촉시킨 후, DPN 기술을 이용하여 표면으로 잉크 물질을 전이시키는 연구를 진행하였다. HDFDTMS 잉크 물질의 dot 어레이 패턴을 안정적으로 제조하였으며, AFM 탐침과 기판 사이의 접촉시간에 따라 패턴 크기가 선형적으로 증가하는 전형적인 DPN의 확산 메커니즘을 보였다.

• Current Photovoltaic Research
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• 제9권4호
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• pp.128-132
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• 2021

Advances in screen printing technology have been led to development of high efficiency silicon solar cells. As a post PERx structure, an n-type wafer-based rear side TOPCon structure has been actively researched for further open-circuit voltage (Voc) improvement. In the case of the metal contact of the TOPCon structure, the poly-Si thickness is very important because the passivation of the substrate will be degraded when the metal paste penetrates until substrate. However, the thin poly-Si layer has advantages in terms of current density due to reduction of parasitic absorption. Therefore, poly-Si thickness and firing temperature must be considered to optimize the metal contact of the TOPCon structure. In this paper, we varied poly-Si thickness and firing peak temperature to evaluate metal induced recombination (Jom) and contact resistivity. Jom was evaluated by using PL imaging technique which does not require both side metal contact. As a results, we realized that the SiN_x deposition conditions can affect the metal contact of the TOPCon structure.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.195-200
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• 2007

최소선폭 $0.1{\mu}m$ 이하의 살리사이드 공정을 상정하여 $10nm-Ni_{0.5}Co_{0.5}/70\;nm-Poly-Si/200\;nm-SiO_2$ 구조로부터 쾌속 열처리를 이용해서 실리사이드 온도를 $600{\sim}1100^{\circ}C$까지 변화시키면서 복합실리사이드를 제조하고 이들의 면저항의 변화와 미세구조의 변화를 면저항 측정기와 TEM 수직단면, 오제이 두께 분석으로 확인하였다. 기존의 동일한 공정으로 제조된 니켈실리사이드에 비해 제안된 니켈 코발트 복합실리사이드는 $900^{\circ}C$까지 저저항을 유지시킬 수 있는 장점이 있었고 20nm 두께의 균일한 실리사이드 층을 폴리실리콘 상부에 형성시킬 수 있었다. 고온 처리시에는 복합실리사이드와 실리콘의 전기적으로 상분리되는 혼합현상으로 고저항 특성이 나타나는 문제를 확인하였다. 제안된 NiCo 합금 박막을 70nm 높이의 폴리실리콘 게이트를 가진 디바이스에 $900^{\circ}C$이하의 실리사이드화 온도에서 효과적으로 산리사이드 공정의 적용이 기대되었다.