• Title/Summary/Keyword: Silicon etching

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Electrical Characteristic of IGZO Oxide TFTs with 3 Layer Gate Insulator

  • Lim, Sang Chul;Koo, Jae Bon;Park, Chan Woo;Jung, Soon-Won;Na, Bock Soon;Lee, Sang Seok;Cho, Kyoung Ik;Chu, Hye Yong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.344-344
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    • 2014
  • Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

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LED Beam Shaping and Fabrication of Optical Components for LED-Based Fingerprint Imager (LED 빔조형에 의한 초소형 이미징 장치의 제조 기술)

  • Joo, Jae-Young;Song, Sang-Bin;Park, Sun-Sub;Lee, Sun-Kyu
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.36 no.10
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    • pp.1189-1193
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    • 2012
  • The Miniaturized Fingerprint Imager (MFI) is a slim optical mouse that can be used as an input device for application to wireless portable personnel communication devices such as smartphones. In this study, we have fabricated key optical components of an MFI, including the illumination optical components and imaging lens. An LED beam-shaping lens consisting of an aspheric lens and a Fresnel facet was successfully machined using a diamond turning machine (DTM). A customized V-shaped groove for beam path banding was fabricated by the bulk micromachining of silicon that was coated with aluminum using the shadow effect in thermal evaporation. The imaging lens and arrayed multilevel Fresnel lenses were fabricated by electron beam lithography and FAB etching, respectively. The proposed optical components are extremely compact and have high optical efficiency; therefore, they are applicable to ultraslim optical systems.

Characteristics of A Diaphragm-Type Fiber Optic Fabry-Perot Interferometric Pressure Sensor Using A Dielectric Film (유전체 박막을 이용한 다이아프램형 광섬유 Fabry-Perot 간섭계 압력센서의 특성)

  • Kim, M.G.;Yoo, Y.W.;Kwon, D.H.;Lee, J.H.;Kim, J.S.;Park, J.H.;Chai, Y.Y.;Sohn, B.K.
    • Journal of Sensor Science and Technology
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    • v.7 no.3
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    • pp.147-153
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    • 1998
  • The strain characteristics of a fiber optic Fabry-Perot pressure sensor with high sensitivity using a $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$ (N/O/N) diaphragm is experimentally investigated. A 600 nm thick N/O/N diaphragm was fabricated by silicon anisotropic etching technology in 44 wt% KOH solution. An interferometric fiber optic pressure sensor has been manufactured by using a fiber optic Fabry-Perot intereferometer and a N/O/N diaphragm. The 2 cm length fiber optic Fabry-Perot interferometers in the continuous length of single mode fiber were produced with two pieces of single mode fiber coated with $TiO_{2}$ dielectric film utilizing the fusion splicing technique. The one end of the fiber optic Fabry-Perot interferometer was bonded to a N/O/N diaphragm. and the other end was connected to an optical setup through a 3 dB coupler. For the N/O/N diaphragm sized $2{\times}2\;mm^{2}$ and $8{\times}8\;mm^{2}$, the pressure sensitivity was measured 0.11 rad/kPa and 1.57 rad/kPa, respectively, and both of the nonlinearities were less than 0.2% FS.

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An Implementation of Temperature Independent Bias Scheme in Voltage Detector (온도에 무관한 전압검출기의 바이어스 구현)

  • Moon, Jong-Kyu;Kim, Duk-Gyoo
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.6
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    • pp.34-42
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    • 2002
  • In this paper, we propose a temperature independent the detective voltage source in voltage detector. The value of a detective voltage source is designed to become m times of silicon bandgap voltage at zero absolute temperature. By properly choosing the temperature coefficient of diode, the temperature coefficient of a concave voltage nonlinearities generated by the ${\Delta}V_{BE}$ section of diode between base and emitter of transistors with a different area can be summed with convex nonlinearities the $V_{BE}$ voltage to achieve the near zero temperature coefficient of the detective voltage source. We designed that the value of a detective voltage can be varied by ${\Delta}V_{BE}$, the $V_{BE}$multiplier circuit and resistor. In order to verify the performance of a proposed detective voltage source, we manufactured the voltage detector IC for 1.9V which is fabricated in $6{\mu}m$ Bipolar technology and measured the operating characteristics, the temperature coefficient of a detective voltage. To reduce the deviation of a detective voltage in the IC process step, we introduced a trimming technology, ion implantation and an isotropic etching. In manufactured IC, the detective voltage source could achieve the stable temperature coefficient of 29ppm/$^{\circ}C$ over the temperature range of -30$^{\circ}C$ to 70$^{\circ}C$. The current consumption of a voltage detector constituted by the proposed detective voltage source is $10{\mu}A$ from 1.9V-supply voltage at room temperature.

The Fabrication of Poly-Si Solar Cells for Low Cost Power Utillity (저가 지상전력을 위한 다결정 실리콘 태양전지 제작)

  • Kim, S.S.;Lim, D.G.;Shim, K.S.;Lee, J.H.;Kim, H.W.;Yi, J.
    • Solar Energy
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    • v.17 no.4
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    • pp.3-11
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    • 1997
  • Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

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$TiO_2$ Thin Film Patterning on Modified Silicon Surfaces by MOCVD and Microcontact Printing Method

  • 강병창;이종현;정덕영;이순보;부진효
    • Proceedings of the Korean Vacuum Society Conference
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    • 2000.02a
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    • pp.77-77
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    • 2000
  • Titanium oxide (TiO2) thin films have valuable properties such as a high refractive index, excellent transmittance in the visible and near-IR frequency, and high chemical stability. Therefore it is extensively used in anti-reflection coating, sensor, and photocatalysis as electrical and optical applications. Specially, TiO2 have a high dielectric constant of 180 along the c axis and 90 along the a axis, so it is highlighted in fabricating dielectric capacitors in micro electronic devices. A variety of methods have been used to produce patterned self-assembled monolayers (SAMs), including microcontact printing ($\mu$CP), UV-photolithotgraphy, e-beam lithography, scanned-probe based micro-machining, and atom-lithography. Above all, thin film fabrication on $\mu$CP modified surface is a potentially low-cost, high-throughput method, because it does not require expensive photolithographic equipment, and it produce micrometer scale patterns in thin film materials. The patterned SAMs were used as thin resists, to transfer patterns onto thin films either by chemical etching or by selective deposition. In this study, we deposited TiO2 thin films on Si (1000 substrateds using titanium (IV) isopropoxide ([Ti(O(C3H7)4)] ; TIP as a single molecular precursor at deposition temperature in the range of 300-$700^{\circ}C$ without any carrier and bubbler gas. Crack-free, highly oriented TiO2 polycrystalline thin films with anatase phase and stoichimetric ratio of Ti and O were successfully deposited on Si(100) at temperature as low as 50$0^{\circ}C$. XRD and TED data showed that below 50$0^{\circ}C$, the TiO2 thin films were dominantly grown on Si(100) surfaces in the [211] direction, whereas with increasing the deposition temperature to $700^{\circ}C$, the main films growth direction was changed to be [200]. Two distinct growth behaviors were observed from the Arhenius plots. In addition to deposition of THe TiO2 thin films on Si(100) substrates, patterning of TiO2 thin films was also performed at grown temperature in the range of 300-50$0^{\circ}C$ by MOCVD onto the Si(100) substrates of which surface was modified by organic thin film template. The organic thin film of SAm is obtained by the $\mu$CP method. Alpha-step profile and optical microscope images showed that the boundaries between SAMs areas and selectively deposited TiO2 thin film areas are very definite and sharp. Capacitance - Voltage measurements made on TiO2 films gave a dielectric constant of 29, suggesting a possibility of electronic material applications.

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