• Title/Summary/Keyword: Silicon etching

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Fabrication and Characteristics of High Efficiency Silicon PERL (passivated emitter and rear locally-diffused cell) Solar Cells (PERL (passivated emitter and rear locally-diffused cell) 방식을 이용한 고효율 Si 태양전지의 제작 및 특성)

  • Kwon, Oh-Joon;Jeoung, Hun;Nam, Ki-Hong;Kim, Yeung-Woo;Bae, Seung-Chun;Park, Sung-Keoun;Kwon, Sung-Yeol;Kim, Woo-Hyun;Kim, Ki-Wan
    • Journal of Sensor Science and Technology
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    • v.8 no.3
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    • pp.283-290
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    • 1999
  • The $n^+/p/p^+$ junction PERL solar cell of $0.1{\sim}2{\Omega}{\cdot}cm$ (100) p type silicon wafer was fabricated through the following steps; that is, wafer cutting, inverted pyramidally textured surfaces etching by KOH, phosphorus and boron diffusion, anti-reflection coating, grid formation and contact annealing. At this time, the optical characteristics of device surface and the efficiency of doping concentration for resistivity were investigated. And diffusion depth and doping concentration for n+ doping were simulated by silvaco program. Then their results were compared with measured results. Under the illumination of AM (air mass)1.5, $100\;mW/cm^2$ $I_{sc}$, $V_{oc}$, fill factor and the conversion efficiency were 43mA, 0.6 V, 0.62. and 16% respectively.

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Development of Casting Furnace for Directional Solidification Ingot (잉곳의 방향성 응고를 위한 주조 로 개발)

  • Ju, Jin-Young;Lee, Seung-Jun;Baek, Ha-Ni;Oh, Hun;Cho, Hyun-Seob;Lee, Choong-Hun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.2
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    • pp.808-816
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    • 2012
  • This paper is the study for the directional solidification of the ingot through the thermal analysis simulation and structural change of casting furnace. With the results of thermal analysis simulation, the silicon as a whole has reached the melting temperature as the retention time 80 min. The best cooling conditions showed at the upper cooling temperature $1,400^{\circ}C$ and cooling time 60min. The fabricated wafers showed the superior etching result at the grain boundary than that of existing commercial wafers. The FTIR measurements of oxygen and carbon impurities were not in the critical value for solar conversion efficiency. The NAA analysis of metal impurities were also detected the total number of 18 different metals, but the concentration distribution showed no significant positional deviations in the same position from the top to the bottom.

The Effects of Corner Transistors in STI-isolated SOI MOSFETs

  • Cho, Seong-Jae;Kim, Tae-Hun;Park, Il-Han;Jeong, Yong-Sang;Lee, Jong-Duk;Shin, Hyung-Cheol;Park, Byung-Gook
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.615-618
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    • 2005
  • In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

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Influence of carrier suppressors on electrical properties of solution-derived InZnO-based thin-film transistors

  • Sim, Jae-Jun;Park, Sang-Hui;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.262-262
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    • 2016
  • 최근 고해상도 디스플레이가 주목받으면서 기존 비정질 실리콘(a-Si)을 대체할 수 있는 재료에 관한 연구가 활발히 진행되고 있다. a-Si의 경우 간단한 공정 과정, 적은 생산비용, 대면적화가 가능하다는 장점이 있지만 전자 이동도가 매우 낮은 단점이 있다. 반면, 산화물 반도체는 비정질 상태에서 전자 이동도가 높으며 큰 밴드갭을 가지고 있어 투명한 특성을 나타낼 뿐만 아니라, 저온공정이 가능하여 기판의 제한이 없는 장점을 가지고 있다. 대표적으로 가장 널리 연구되고 있는 산화물 반도체는 a-IGZO(amorphous indium-gallium-zinc oxide)이다. 그러나 InZnO(IZO) 기반의 산화물 반도체에서 carrier suppressor 역할을 하는 Ga(gallium)은 수요에 대한 공급이 원활하지 못하여 비싸다는 단점이 있다. 그러므로 경제적이면서 a-IGZO와 유사한 전기적 특성을 나타낼 수 있는 suppressor 물질이 필요하다. 따라서 본 연구에서는 IZO 기반의 산화물 반도체에서 Ga을 Hf(hafnium), Zr(zirconium), Si(silicon)으로 대체하여 용액증착(solution-deposition) 공정으로 각각의 채널층을 형성한 back-gate type의 박막 트랜지스터(thin-film transistor, TFT) 소자를 제작하였다. 용액증착 공정은 물질의 비율을 자유롭게 조절할 수 있고, 대기압의 조건에서도 공정이 가능하기 때문에 짧은 공정시간과 저비용의 장점이 있다. 제작된 소자는 p-type Si 위에 게이트 절연막으로 100 nm의 열산화막이 성장된 기판을 사용하였다. 표준 RCA 클리닝 후에 각 solution 물질을 spin coating 방식으로 증착하였다. 이후, photolithography, develop, wet etching의 과정을 거쳐 채널층 패턴을 형성하였다. 또한, 산화물 반도체의 전기적 특성을 향상시키기 위해서 후속 열처리 과정(post deposition annealing, PDA)은 필수적이다. CTA 방식은 높은 열처리 온도와 긴 열처리 시간의 단점이 있다. 따라서, 본 연구에서는 $100^{\circ}C$ 이하의 낮은 온도와 짧은 열처리 시간의 장점을 가지는 MWI (microwave irradiation)를 후속 열처리로 진행하였다. 그 결과, 각 물질로 구현된 소자들은 기존 a-IGZO와 비교하여 적은 양의 carrier suppressor로도 우수한 전기적 특성 및 안정성을 얻을 수 있었다. 따라서, Si, Hf, Zr 기반의 산화물 반도체는 기존의 Ga을 대체하여 저비용으로 디스플레이를 구현할 수 있는 IZO 기반 재료로 기대된다.

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Fabrication and characteristics of micro-machined thermoelectric flow sensor (실리콘 미세 가공을 이용한 열전형 미소유량센서 제작 및 특성)

  • Lee, Young-Hwa;Roh, Sung-Cheoul;Na, Pil-Sun;Kim, Kook-Jin;Lee, Kwang-Chul;Choi, Yong-Moon;Park, Se-Il;Ihm, Young-Eon
    • Journal of Sensor Science and Technology
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    • v.14 no.1
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    • pp.22-27
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    • 2005
  • A thermoelectric flow sensor for small quantity of gas flow rate was fabricated using silicon wafer semiconductor process and bulk micromachining technology. Evanohm R alloy heater and chromel-constantan thermocouples were used as a generation heat unit and sensing parts, respectively. The heater and thermocouples are thermally isolated on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$ laminated membrane. The characteristics of this sensor were observed in the flow rate range from 0.2 slm to 1.0 slm and the heater power from 0.72 mW to 5.63 mW. The results showed that the sensitivities $(({\partial}({\Delta}V)/{\partial}(\dot{q}));{\;}{\Delta}V$ : voltage difference, $\dot{q}$ : flow rate) were increased in accordance with heater power rise and decreasing of flow rate.

Design, Fabricaiton and Testing of a Piezoresistive Cantilever-Beam Microaccelerometer for Automotive Airbag Applications (에어백용 압저항형 외팔보 미소 가속도계의 설계, 제작 및 시험)

  • Ko, Jong-Soo;Cho, Young-Ho;Kwak, Byung-Man;Park, Kwan-Hum
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.20 no.2
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    • pp.408-413
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    • 1996
  • A self-diagnostic, air-damped, piezoresitive, cantilever-beam microaccelerometer has been designed, fabricated and tested for applications to automotive electronic airbag systems. A skew-symmetric proof-mass has been designed for self-diagnostic capability and zero transverse sensitivity. Two kinds of multi-step anisotropic etching processes are developed for beam thickness control and fillet-rounding formation, UV-curing paste has been used for sillicon-to-glass bounding. The resonant frequency of 2.07kHz has been measured from the fabricated devices. The sensitivity of 195 $\mu{V}$/g is obtained with a nonlinearity of 4% over $\pm$50g ranges. Flat amplitude response and frequency-proportional phase response have been obserbed, It is shown that the design and fabricaiton methods developed in the present study yield a simple, practical and effective mean for improving the performance, reliability as well as the reproducibility of the accelerometers.

Fabrication of Micron-sized Organic Field Effect Transistors (마이크로미터 크기의 유기 전계 효과 트랜지스터 제작)

  • Park, Sung-Chan;Huh, Jung-Hwan;Kim, Gyu-Tae;Ha, Jeong-Sook
    • Journal of the Korean Vacuum Society
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    • v.20 no.1
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    • pp.63-69
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    • 2011
  • In this study, we report on the novel lithographic patterning method to fabricate organic thin film field effect transistors (OTFTs) based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30 nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce $Al_2O_3$ film grown via atomic layer deposition method onto pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated micron sized pentacene FETs and measured their electrical characteristics.

3D Lithography using X-ray Exposure Devices Integrated with Electrostatic and Electrothermal Actuators

  • Lee, Kwang-Cheol;Lee, Seung S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.4
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    • pp.259-267
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    • 2002
  • We present a novel 3D fabrication method with single X-ray process utilizing an X-ray mask in which a micro-actuator is integrated. An X-ray absorber is electroplated on the shuttle mass driven by the integrated micro-actuator during deep X-ray exposures. 3D microstructures are revealed by development kinetics and modulated in-depth dose distribution in resist, usually PMMA. Fabrication of X-ray masks with integrated electrothermal xy-stage and electrostatic actuator is presented along with discussions on PMMA development characteristics. Both devices use $20-\mu\textrm{m}$-thick overhanging single crystal Si as a structural material and fabricated using deep reactive ion etching of silicon-on-insulator wafer, phosphorous diffusion, gold electroplating, and bulk micromachining process. In electrostatic devices, $10-\mu\textrm{m}-thick$ gold absorber on $1mm{\times}1mm$ Si shuttle mass is supported by $10-\mu\textrm{m}-wide$, 1-mm-long suspension beams and oscillated by comb electrodes during X-ray exposures. In electrothermal devices, gold absorber on 1.42 mm diameter shuttle mass is oscillated in x and y directions sequentially by thermal expansion caused by joule heating of the corresponding bent beam actuators. The fundamental frequency and amplitude of the electrostatic devices are around 3.6 kHz and $20\mu\textrm{m}$, respectively, for a dc bias of 100 V and an ac bias of 20 VP-P (peak-peak). Displacements in x and y directions of the electrothermal devices are both around $20{\;}\mu\textrm{m}$at 742 mW input power. S-shaped and conical shaped PMMA microstructures are demonstrated through X-ray experiments with the fabricated devices.

Thermal oxidation and oxidation induced stacking faults of tilted angled (100) silicon substrate (저탈각 (100) Si 기판의 열산화 및 적층 결함)

  • 김준우;최두진
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.6 no.2
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    • pp.185-193
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    • 1996
  • $2.5^{\circ}\;and\;5^{\circ}$ tilted (100) Si wafer were oxidized in dry oxygen, and the differences in thermal oxidation behavior and oxidation induced stacking faults (OSF) between specimens were investigated. Ellipsometer measurements of the oxide thickness produced by oxidation in dry oxygen from 900 to $1200^{\circ}C$ showed that the oxidation rates of the tilted (100) Si were more rapid than those of the (100) Si and the differences between them decreased as the oxidation temperature increased. The activation energies based on the parabolic rate constant, B for (100) Si, $2.5^{\circ}$ off (100) Si and $5^{\circ}$ off (100) Si were 27.3, 25.9, 27.6 kcal/mol and those on the linear rate constant, B/A were 58.6, 56.6, 57.6 kcal/mol, respectively. Also, considerable decrease in the density of oxidation induced stacking faults for the $5^{\circ}$ off (100) Si was observed through optical microscopy after preferentially etching off the oxide layer, and the angle of stacking faults were changed with tilted angles.

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Improvement of Surface-enhanced Raman Spectroscopy Response Characteristics of Nanoporous Ag Metal Thin Film with Surface Texture Structures (표면 요철구조를 적용한 나노 다공성 Ag 금속박막의 SERS 응답 특성 개선)

  • Kim, Hyeong Ju;Kim, Bonghwan;Lee, Dongin;Lee, Bong-Hee;Cho, Chanseob
    • Journal of Sensor Science and Technology
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    • v.29 no.4
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    • pp.255-260
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    • 2020
  • In this study, we developed a method of improving the surface-enhanced Raman spectroscopy (SERS) response characteristics by depositing a nanoporous Ag metal thin film through cluster source sputtering after forming a pyramidal texture structure on the Si substrate surface. A reactive ion etching (RIE) system with a metal mesh inside the system was used to form a pyramidal texture structure on the Si surface without following a complicated photolithography process, unlike in case of the conventional RIE system. The size of the texture structure increased with the RIE process time. However, after a process time of 60 min, the size of the structure did not increase but tended to saturate. When the RF power increased from 200 to 250 W, the size of the pyramidal texture structure increased from 0.45 to 0.8 ㎛. The SERS response characteristics were measured by depositing approximately 1.5 ㎛ of nanoporous Ag metal thin film through cluster sputtering on the formed texture structure by varying the RIE process conditions. The Raman signal strength of the nanoporous Ag metal thin film deposited on the Si substrate with the texture structure was higher than that deposited on the general silicon substrate by up to 19%. The Raman response characteristics were influenced by the pyramid size and the number of pyramids per unit area but appeared to be influenced more by the number of pyramids per unit area. Therefore, further studies are required in this regard.