• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.666-670
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• 2013

Recovery method of silicon wafer from defective products generated from manufacturing process of silicon solar cells was studied. The removal effect of the N layer and antireflection coating (ARC) of the waste solar cell were investigated at room temperature ($25^{\circ}C$) by variation of concentration of $H_3PO_4$, $NH_4HF_2$, and concentration and types of chelating agent. Removal efficiency was the best in the conditions; 10 wt% $H_3PO_4$ 2.0 wt% $NH_4HF_2$, 1.5 wt% Hydantoin. Increasing the concentration of $H_3PO_4$, the surface contamination degree was increased and the thickness of the silicon wafe became thicker than the thickness before surface treatment because of re-adsorption on the silicon wafer surface by electrostatic attraction of the fine particles changed to (+). The etching method by mixed solution of $H_3PO_4$-$NH_4HF_2$-chelating agents was expected to be great as an alternative to conventional RCA cleaning methods and as the recycle method of waste solar cells, because all processes are performed at room temperature, the process is simple, and less wastewater, the removal efficiency of the surface of the solar cell was excellent.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Korean Chemical Engineering Research
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• v.45 no.2
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• pp.203-207
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• 2007

In this paper efficient method for particle removal from silicon wafers by usage of HF and ozone was studied. It was found that at least 0.3 vol% concentration of HF was required for particle removal and removal efficiency increased with the application of megasonic in ozonated water. Additional cleaning with minute amount of ammonia (0.01 vol%) after HF/Ozone step showed over 99% in removal efficiency. It is proposed that the superior cleaning efficiency of HF-Ozone-ammonia is due to micro-etching of silicon surface and impediment of particle re-adsorption in alkali environment. Compared to SC-1 cleaning method micro roughness has also been slightly improved. Therefore it is expected that HF-ozone-ammonia cleaning method is a viable alternative to the conventional wet cleaning methods.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.30 no.5
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• pp.163-167
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• 2020

Ring-shaped SiC (Silicon carbide) polycrystals used as an inner material in semiconductor etching equipment was manufactured using the PVT (Physical Vapor Transport) method. A graphite cylinder structure was placed inside the graphite crucible to grow a ring-shaped SiC polycrystal by the PVT method. The crystal polytype of grown crystal were analyzed using a Raman and an UVF (Ultra Violet Fluorescence) analysis. And the microstructure and components of SiC crystal were identified by a SEM (Scanning Electron Microscope) and EDS (Energy Disruptive Spectroscopy) analyses. The grain size and growth rate of SiC polycrystals fabricated by this method was varied with temperature variation in the initial stage of growth process.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.3
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• pp.428-435
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• 2002

Pyroelectric $Pb(Zr_{0.3}Ti_{0.7})O_3$ (PZT30/70) thin film IR detectors has been fabricated and characterised. The PZT30/70 thin film was deposited onto $Pt/Ti/Si_3N_4/SiO_2/Si$ substrate by the sol-gel process. Four different substrate conditions were studied for their effects on the pyroelectric responses of the IR detectors. The substrate conditions were the combinations of the Si etching and the Pt/Ti patterning. In the Si etched substrate, the $Si_3N_4/SiO_2$ composite layer was used as silicon etch-stop, and was used as the membrane to support the PZT pyroelectric film element as well. The measured pyroelectric current and voltage responses of detectors fabricated on the micro-machined thin $Si_3N_4/SiO_2$ membrane were two orders higher than those of the detectors on the bulk-silicon. For detectors on the membrane substrate, the Pt/Ti patterned detectors showed a 2-times higher pyroelectric response than that of not-patterned detectors. On the other hand, the pyroelectric response of the detectors on the not-etched Si substrate was almost the same, regardless of the Pt/Ti patterning. It was also found that the rise time strongly depended on the substrate thickness: the thicker the substrate was, the longer the rise-time.

• Korean Chemical Engineering Research
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• v.54 no.4
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• pp.459-464
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• 2016

In this study, the electrochemical characteristics of porous silicon/carbon composite anode were investigated to improve the cycle stability and rate performance in lithium ion batteries. In this study, the effect of TEOS and $NH_3$ concentration, mixing speed and temperature on particle size of nano silica was investigated using $St{\ddot{o}}ber$ method. Nano porous Si/C composites were prepared by the fabrication processes including the synthesis of nano $SiO_2$, magnesiothermic reduction of nano $SiO_2$ to obtain nano porous Si by HCl etching, and carbonization of phenolic resin. Also the electrochemical performances of nano porous Si/C composites as the anode were performed by constant current charge/discharge test, cyclic voltammetry and impedance tests in the electrolyte of $LiPF_6$ dissolved inorganic solvents (EC:DMC:EMC=1:1:1vol%). It is found that the coin cell using nano porous Si/C composite has the capacity of 2,006 mAh/g and the capacity retention ratio was 55.4% after 40 cycle.

• Journal of the Korean Society for Heat Treatment
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• v.31 no.1
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• pp.6-11
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• 2018

The anodic oxidation behavior of Si-containing aluminum alloy for diecasting was investigated. Especially, the property changes during anodization both on aluminum 1050 and 9 weight percentage silicon containing aluminum (Al-9Si) alloys were analyzed by the static current test. In order to fabricate a uniform anodic oxidation film by effect of Al-Si compound, nitric acid containing hydrofluoric acid had been used as a desmutter for aluminum alloy after alkaline etching. It was found that the level of voltage of Al-9Si alloy during the static current test was almost as double as higher than aluminum 1050 through anodization. By adding hydrofluoric acid in the nitric acid electrolyte, the silicon compound on the surface was removed, and the optimum amount of added hydrofluoric acid could be derived. It was also observed that the size of silicon compound formed on the surface could be refined by heat treatment at $500^{\circ}C$ and followed water quenching.

• Bulletin of the Korean Chemical Society
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• v.35 no.1
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• pp.35-38
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• 2014

Herein, we report on the preparation of red fluorescent Si nanoparticles stabilized with styrene. Nano-sized Si particles emit fluorescence under UV excitation, which could be used to open up new applications in the fields of optics and semi-conductor research. Unfortunately, conventional methods for the preparation of red fluorescent Si nanoparticles suffer from the lack of a fully-established standard synthesis protocol. A common initial approach during the preparation of semi-conductors is the etching of crystalline Si wafers in a HF/ethanol/$H_2O$ bath, which provides a uniformly-etched surface of nanopores amenable for further nano-sized modifications via tuning of various parameters. Subsequent sonication of the etched surface crumbles the pores on the wafer, resulting in the dispersion of particles into the solution. In this study, we use styrene to occupy these platforms to stabilize the surface. We determine that the liberated silicon particles in ethanol solution interact with styrene, resulting in the substitution of Si-H bonds with those of Si-C as determined via UV photo-catalysis. The synthesized styrene-coated Si nanoparticles exhibit a stable, bright, red fluorescence under excitation with a 365 nm UV light, and yield approximately 100 mg per wafer with a synthesis time of 2 h. We believe this protocol could be further expanded as a cost-effective and high-throughput standard method in the preparation of red fluorescent Si nanoparticles.

• Journal of the Korean Solar Energy Society
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• v.31 no.1
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• pp.37-43
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• 2011

In this paper, the optimized doping condition of crystalline silicon solar cells with $156{\times}156\;mm^2$ area was studied. To optimize the drive-in temperature in the doping process, the other conditions except variable drive-in temperature were fixed. These conditions were obtained in previous studies. After etching$7\;{\mu}m$ of the surface to form the pyramidal structure, the silicon nitride deposited by the PECVD had 75~80nm thickness and 2 to 2.1 for a refractive index. The silver and aluminium electrodes for front and back sheet, respectively, were formed by screen-printing method, followed by firing in 400-425-450-550-$850^{\circ}C$ five-zone temperature conditions to make the ohmic contact. Drive-in temperature was changed in range of $830^{\circ}C$ to $890^{\circ}C$to obtain the sheet resistance $30{\sim}70\;{\Omega}/{\box}$ with $10\;\Omega}/{\box}$ intervals. Solar cell made in $890^{\circ}C$ as the drive-in temperature revealed 17.1% conversion efficiency which is best in this study. This solar cells showed $34.4\;mA/cm^2$ of the current density, 627 mV of the open circuit voltage and 79.3% of the fill factor.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.