• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.9
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• pp.789-794
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• 2014

The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Journal of Digital Convergence
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• v.14 no.7
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• pp.331-337
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• 2016

The purpose of this study is to provide a method to visualize the sound data to the three-dimensional image. The visualization of the sound data is performed according to the algorithm set after production of the text-based script that form the channel range of the sound data. The algorithm consists of a total of five levels, including setting sound channel range, setting picture frame for sound visualization, setting 3D image unit's property, extracting channel range of sound data and sound visualization, 3D visualization is performed with at least an operation signal input by the input device such as a mouse. With the sound files with the amount an animator can not finish in the normal way, 3D visualization method proposed in this study was highlighted that the low-cost, highly efficient way to produce creative artistic image by comparing the working time the animator with a study presented method and time for work. Future research will be the real-time visualization method of the sound data in a way that is going through a rendering process in the game engine.

• Nuclear Engineering and Technology
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• v.26 no.4
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• pp.555-561
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• 1994

The program of performing a fast and automatic analysis of gamma ray spectra obtained by a Multi-Channel Analyzer (MCA) is developed for the surveillance of the nuclear fuel integrity. The integrity of the nuclear fuel is confirmed by the measurement of the radiation level of the reactor coolant through the real time monitoring and the periodic sampling analysis. In Yonggwang nuclear power plane 3 and 4, the Process Radiation Monitoring System (PRMS), which is a real time monitoring system, provides a measure of the fuel integrity. Currently, its spectrometer channel can identify only one radionuclide at a time since the signal processing unit of the spectrometer channel is a Single Channel Analyzer (SCA). To improve the PRMS, it is necessary to substitute the MCA for the SCA The program is operated in a real time mode and an on-demand mode, and automatically performed for all procedures. The test results by using the National Bureau of Standards (NBS) mixed standard source are in good agreement with those from Canberra System 100 which is a commercial MCA Consequently, the developed program seems to be employed for automatic monitoring of gamma rays in nuclear power plants.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.192-198
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• 2021

The battery's State of Health (SOH) is a critical parameter in the process of battery use, as it represents the Remaining Useful Life (RUL) of the battery. Electrochemical Impedance Spectroscopy (EIS) is a widely used technique in observing the state of the battery. The measured impedance at certain frequencies can be used to evaluate the state of the battery, as it is intimately tied to the underlying chemical reactions. In this work, a low-cost portable EIS instrument is developed on the basis of the ARM Cortex-M4 Microcontroller Unit (MCU) for measuring the impedance spectrum of Li-ion battery packs. The MCU uses a built-in DAC module to generate the sinusoidal sweep perturbation signal. Moreover, it performs the dual-channel acquisition of voltage and current signals, calculates impedance using a Digital Lock-in Amplifier (DLA), and transmits the result to a PC. By using LabVIEW, an interface was developed with the real-time display of the EIS information. The developed instrument was suitable for measuring the impedance spectrum of the battery pack up to 1000 V. The measurement frequency range of the instrument was from 1 hz to 1 Khz. Then, to prove the performance of the developed system, the impedance of a Samsung SM3 battery pack and a Bexel pouch module were measured and compared with those obtained by the commercial instrument.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.31-38
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• 2008

Ad-Hoc network is a network architecture which has no backbone network and is deployed temporarily and rapidly in emergency or war without fixed mobile infrastructures. All communications between network entities are carried in ad-hoc networks over the wireless medium. Due to the radio communications being extremely vulnerable to propagation impairments, connectivity between network nodes is not guaranteed. Therefore, many new algorithms have been studied recently. This study proposes the secondary header approach to the cluster based routing protocol (CBRP). The primary header becomes abnormal status so that the primary header can not participate in the communications between network entities, the secondary header immediately replaces the primary header without selecting process of the new primary header. This improves the routing interruption problem that occurs when a header is moving out from a cluster or in the abnormal status. The performances of proposed algorithm ACBRP(Advanced Cluster Based Routing Protocol) are compared with CBRP. The cost of the primary header reelection of ACBRP is simulated. And results are presented in order to show the effectiveness of the algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.1-8
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• 2008

We propose how to program the off-line buffing robot path along shoes' outsole shape in the footwear buffing process by a 5-axis microscribe system like robot mechanism. The microscribe system we developed consists of a 5-axis robot link with a turn table, a signal processing unit, PC and an application software program. Itmakes a robot path on the shoes' upper in accordance with the movement of a microscribe with many joints. The developed system calculates the encoder pulse values for the microscribe arm's rotation and transmits the angle pulse values to the PC through a processing unit. Denavit-Hartenberg's(D-H) direct kinematics is used to make the global coordinate from microscribe joint one. Problems with the microscribe's kinematics can be solved efficiently and systematically by D-H representation. With the coordinate values calculated by D-H equation, our system can draw a buffing gauge-line on the upper sole. We obtain shoes' outline points, which are 2 outlines coupled with the points and the normal vector based on the points. By applying the system to the buffing robot in a flexible manufacturing system, it can be used effectively to program the path of a real buffing robot.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Journal of IKEEE
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• v.26 no.3
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• pp.510-514
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• 2022

In this paper, we propose the development of high-sensitivity low-end radiation measuring sensor module. The proposed measurement sensor module is a scintillator + photomultiplier(SiPM) sensor optimization structure design, amplification and filter and control circuit design for sensor driver, control circuit design including short-distance communication, sensor mechanism design and manufacturing, and GUI development applied to prototypes consists of, etc. The scintillator + photomultiplier(SiPM) sensor optimization structure design is designed by checking the characteristics of the scintillator and the photomultiplier (SiPM) for the sensor structure design. Amplification, filter and control circuit design for sensor driver is designed to process fine scintillation signal generated by radiation with a scintillator using SiPM. Control circuit design including short-distance communication is designed to enable data transmission through MCU design to support short-range wireless communication function and wired communication support. The sensor mechanism design and manufacture is designed so that the glare generated by wrapping a reflective paper (mirroring) on the outside of the plastic scintillator is reflected to increase the efficiency in order to transmit the fine scintillation signal generated from the plastic scintillator to the photomultiplier(SiPM). The GUI development applied to the prototype expresses the date and time at the top according to each screen and allows the measurement unit and time, seconds, alarm level, communication status, battery capacity, etc. to be expressed. In order to evaluate the performance of the proposed system, the results of experiments conducted by an authorized testing institute showed that the radiation dose measurement range was 30 𝜇Sv/h ~ 10 mSv/h, so the results are the same as the highest level among products sold commercially at domestic and foreign. In addition, it was confirmed that the measurement uncertainty of ±7.4% was measured, and normal operation was performed under the international standard ±15%.