• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.828-835
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• 2001

Novel bipolar transresistance amplifier(TRA) and its offset-compensated TRA for high-performance current-mode signal processing are described. The TRA consist of two current follower for a current inputs, a current summer for the current-difference, a resistor for the current to voltage converter, and a voltage follower for the voltage output. The offset-compensated TRA adopts diode-connected npn and pnp transistor to reduce offset voltage in the TRA. The simulation results show that the TRA has impedance of 0.5 Ω at the input and the output terminal. The offset voltages at these terminals is 40 mV The offset-compensated TRA has the offset voltage of 1.1 mV and the impedance of 0.25 Ω. The 3-dB cutoff frequency is 40 MHz for the two TRA＇s when used as a current to voltage converter with unit-gain transresistance. The power dissipation is 11.25 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1310-1318
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• 1998

Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.89-91
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• 2007

In this paper, a remote monitoring system of wind-photovoltaic hybrid generation system using mobile phone and internet has been developed. Many kinds of data can be acquired, analyzed and saved automatically by this system. The hybrid system is composed of 1[kW] PV with DC/DC converter, battery banks and 5[kW] wind power system with power inductor and AC/DC converter. In addition, wind monitoring sensors, voltage and current meters, current transformers and potential transformers are used as accessory instruments. All of these signals are fed into DAQ (Data Acquisition) board after converting the data which have been processed by many types of converters, dividing circuits and signal conditioning circuits. These data can not only be displayed on a computer, transmitted using the server program to remote computer and saved on a computer as a file day by day but also be sent as a CDMA message. The monitored-data can be downloaded, analyzed and saved from server program in real-time via mobile phone or internet at a remote place. All of the programs were designed with LabVIEW software.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Journal of the Korean Society for Nondestructive Testing
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• v.29 no.2
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• pp.145-152
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• 2009

Currently almost all in-service-inspection techniques, applied in domestic nuclear power plants, are partial to field inspection technique. These kinds of techniques are related to managing nuclear power plants by the operation of foreign-produced inspection devices. There have been so many needsfor development of native in-service-inspection device because there is no native diagnosis device for nuclear power plant inspection yet in Korea. In this research, we developed several core techniques to make an automated ultrasonic pipe inspection system for nuclear power plants. A high performance multi-channel ultrasonic pulser/receiver module, an A/D converter module and a digital main CPU module were developed and the performance of the developed modules was verified. The S/N ratio, noise level and signal acquisition performance of the developed modules showed proper level as we designed in the beginning.

• Journal of Biomedical Engineering Research
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• v.28 no.4
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• pp.539-548
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• 2007

In the paper, a wireless charger with the function of auto-shutdown for fully implantale middle ear hearing devices (F-IMEHD) has been designed. The wireless charger can communicate with an implant module to be turned off automatically shutdown after an internal rechargeable battery has been fully-charged by electromagnetic coupling using two coils. For the communication with an implant module, the wireless charger uses the load shift keying (LSK) method. But, the variation of the mutual inductance due to the different distance between two coils can cause the communication error in receiving the fully-charged signal from an implant module. To solve the problem, the implemented wireless charger has a variable reference generator for LSK communication. The wireless charger generates proper level of the reference voltage for a comparator using an ADC (analog-to-digital converter) and a DAC (digital-to-analog converter). Through the result of experiment, it has been confirmed that the presented wireless charger can detect signals from implantable module. And wireless charger can stop generating electromagnetic flux after an implanted battery has been fully charged in spite of variable coil distance according to different skin thickness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.569-571
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• 2007

In this paper, hem antenna composed of rectangular hern, circular polarizer and straight-type mode convertor is designed and fabricated. The circular polarizer is designed as a dielectric type having broadband characteristic, and it is inserted into the rectangular hem with $45^{\circ}$ inclination. The straight-type mode convertor has a terrace-type structure in order to convert the TEM mode signal of coaxial cable to the TE mode of rectangular waveguide, and this structure minimizes conversion loss. Fabricated hem antenna operates at $30.085\sim30.885GHz$ and has VSWR < 1.5, Axial ratio < 1.0dB and antenna gain of $6.7\sim7.0dBi$ in the band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.59-64
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• 2006

The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.