• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.11
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• pp.536-543
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• 2003

In this paper, we describe a unique self oscillating and mixing (SOM) down-converter design using a modified defected ground structure (DGS). The proposed SOM converter is consisted of self-oscillator, which can produce negative resistance and select resonance frequency, RF matching circuit, and IF low pass filter. As the advantage of this SOM converter can mix LO and RF signals as well as inducing LO signal with only one active device. it is designed as a simple structure and the low cost. Also, there is easy advantage to be applied in RFIC/MMIC technology because it offers excellent phase noise performance in spite of using micro-strip structure. The LO signal for the proposed SOM converter is designed at 1㎓ and RF frequency was chosen to be 800MHz. The achieved conversion loss and phase noise performances of the implemented SOM converter are 15㏈ and -95dBc/Hz at 100KHz offset frequency respectively. The equivalent circuit parameters for DGS are extracted by using a three dimensional EM simulator and simple circuit analysis method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.129-137
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• 2017

In this paper, we propose a digital controller design methodology for an LLC resonant converter which has been widely used due to the advantages of low switching loss and high efficiency. We establish a mathematical model of an LLC resonant converter using the extended describing function concept and propose a controller design method based on the Ziegler Nichols control parameter tuning criteria. The voltage controller of an LLC resonant converter is designed based on the derived small signal model and the performance of the controller is verified by MATLAB simulations. The validity and the control performance of the designed voltage controller for the LLC resonant converter is analyzed through some simulations for the case of load variations and circuit modeling errors.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.1
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• pp.54-60
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• 2020

A digital current control scheme using virtual d-q transformation for a boost single-phase power factor correction (PFC) converter is proposed. The use of virtual d-q transformation in single-phase power converters is known to improve current control performance. However, the conventional virtual d-q transformation-based digital current control scheme cannot be directly applied to the boost single-phase PFC converter because the current and average voltage waveforms of the inductor used in the converter are not sinusoidal. To cope with this problem, this study proposes a virtual sinusoidal signal generation method that converts the current and average voltage waveform of the inductor into a sinusoidal waveform synchronized with the grid. Simulation and experimental results are provided to show that the virtual d-q transformation-based digital current control is successfully applied to the boost single-phase PFC converter with the aid of the proposed virtual sinusoidal signal generation method.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.6
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• pp.1058-1063
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• 2010

In this paper, we designed self-frequency synchronizing circuit using image rejection mixer(IRM) and single-sideband(SSB) up-converter which can effectively eliminate the image frequencies occurred in multi-channel super-heterodyne receivers and help us to match inter-channel phase. Also the self-frequency synchronizing circuit simplifies system because there need no extra devices for making intermediate frequency(IF) by creating the local signal within several nanoseconds by means of generating the same frequency of IF signal and modulating radio frequency(RF) signal. We adopt the limiting amplifier for the purpose of protecting the circuit from spurious signals which come from the front end side having wide instantaneous bandwidth characteristics and constantly injecting same level into the input local signal of IRM. The IRM we fabricated has image rejection ratio of 27dB, which is good over 7dB for foreign company's. Also, the SSB up-converter we fabricated has 1dB compression point of 18dBm, which is good over 16dB for foreign company's. And the size is compact about one-forth.

• Proceedings of the KSME Conference
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• 2001.06b
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• pp.42-47
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• 2001

Analyzing the ECG signal, we can find heart disease, for example, arrhythmia and myocardial infarction, etc. Particularly, detecting arrhythmia is more important, because serious arrhythmia can take away the life from patients within ten minutes. In this paper, we would like to introduce the signal processing for ECG analysis and the device made for wireless communication of ECG data. In the signal processing, the wavelet transform decomposes the ECG signal into high and low frequency components using wavelet function. Recomposing the high frequency bands including QRS complex, we can detect QRS complex and eliminate the noise from the original ECG signal. To recognize the ECG signal pattern, we adopted the polynomial approximation partially and statistical method. The ECG signal is divided into small parts based on QRS complex, and then, each part is approximated to the polynomials. Comparing the approximated ECG pattern with the database, we can detect and classify the heart disease. The ECG detection device consists of amplifier, filters, A/D converter and RF module. After amplification and filtering, the ECG signal is fed through the A/D converter to be digitalized. The digital ECG data is transmitted to the personal computer through the RF transceiver module and serial port.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.61-64
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• 2000

In this paper, we design up-down converter for asynchronous IMT-2000 base station using W-CDMA(Wideband Code Division Multiple Access) technology. This up-down converter(UDC) has AGC (Automatic Gain Control), TPTL(Transmitting Power Tracing Loop), RSSI(Received Signal Strength Indicator) function. And for the cell control of BS(Base Station), breathing, blossoming, wilting function also available. This UDC has diversity structure for better performance.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.619-621
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• 1996

This paper presents the study on the development of the power factor correction convener with ZVT Boost converter, which is better than the conventional PWM Boost converter to increase the switching frequency for high density and lower stress of switch. A simple DC and small signal model for the power factor correction converter with constant switching frequency is derived. The guide line for design of controller is summarized.