• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.358-361
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• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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• pp.309-313
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• 1990

Pulse width modulation using discontinuous conduction modes are applied to a full-bridge series resonant converter to regulate the output from no load to full load with low switching loss and a narrow range of frequency variation. Finally, a simple nonlinear discrete-time dynamic model for this proposed converter is derived using approximation. This discrete time model is linearized and a general input - output transfer function for the propelled converter is derived.

• 천문학논총
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• 제22권3호
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• pp.83-87
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• 2007

We designed the Intermediate Frequency(IF) distributor for multi beam backend system and manufactured Voltage to Frequency Converter(VFC) to measure the multi-beam receiver performance. Multi beam receiver has 15 channel receivers and can get 15 spectrums at once. The multi beam receiver has more observation efficiency than single beam receiver. We manufactured the 15 IF distributors to distribute IF signal for Autocorrelation spectrometer that is radio signal processor. Also, we manufactured the VF Converter to test the performance measurement of receiver for Korea VLBI Network(KVN) system which is under-construct in Seoul, Ulsan and Jeju. As a result of performance measurement, we could obtain linearity of 99.4% on the input power vs output frequency and measured the operating range of input frequency.

• Journal of Power Electronics
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• 제16권5호
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• pp.1802-1812
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• 2016

Cross regulation is a key technical issue of single-inductor multiple-output (SIMO) DC-DC converters. This paper investigates the cross regulation in single-inductor dual-output (SIDO) Buck converters with continuous conduction mode (CCM) operation. The expressions of the DC voltage gain, control to the output transfer function, cross regulation transfer function, cross coupled transfer function and impedance transfer function of the converter are presented by the time averaging equivalent circuit approach. A small signal model of a SIDO CCM Buck converter is built to analyze this cross regulation. The laws of cross regulation with respect to various load conditions are investigated. Simulation and experiment results verify the theoretical analysis. This study will be helpful for converter design to reduce the cross regulation. In addition, a control strategy to reduce cross regulation is performed.

• 전자공학회논문지A
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• 제30A권12호
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• 한국광학회지
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• 제14권3호
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• pp.215-218
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• 2003

2R 광/전/광 파장변환기는 이미 검증된 기술을 사용하여 간단히 구현할 수 있으며 데이터 전송율을 제한하지 않는다는 장점이 있다. 그러나, 이 방식은 각 파장변환기를 통과하면서 타이밍 지터 성분이 계속 누적되어 cascadability가 제한된다 본 논문에서는 통상적인 정현파 신호 모델 대신 보다 현실적인 비선형 신호 모델을 제안하여 시스템 성능에 미치는 타이밍 지터의 영향 및 2R 광/전/광 파장변환기의 cascadability를 이론적으로 분석하였으며, 40-km re-circulation loop 실험 장치에서 10 Gb/s 신호에 대한 cascadability를 측정하여 계산 결과와 비교하였다.

• 한국통신학회논문지
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• 제31권8C호
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• pp.806-815
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• 2006

디지털 변복조 장치에는 디지털 신호의 표본화 속도를 변환시키는 표본화 속도 변환기(SRC: sample rate converter)가 필요한데, 여기에 사용되는 저역필터의 구현 문제를 연구하였다. 표본화 속도 변환율이 클 경우에는 저역필터의 신호처리 연산량이 많아져서 구현에 부담이 되므로 연산량을 감소시키는 방안이 중요하다. 본 논문에서는 이 필터를 2 단의 직렬 필터로 분할하여 구현하는 설계 방법을 제시하였고, 1 단 구조의 단일 필터로 구현하였을 경우에 비교하여 신호처리 연산량이 감소되는 것을 확인하였다. 표본화 속도 변환율이 증가할수록 2 단분할 방안에 의한 연산량 감소 효과는 증가하며, 변환율이 32 에서는 72 %까지 감소되는 것을 확인하였다. 변환율을 2 단으로 분할함에 있어서도 인수의 조합에 따라서 감소 효과가 다르게 나타났으므로, 여러 변환율에 대하여 최적 성능의 분할율을 조사하였다. 저역필터는 다상 필터 구조를 갖는 FIR 필터를 대상으로 하였으며, 필터계수의 설계는 Parks-McCllelan 알고리즘을 이용하였다.

• 전기학회논문지
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• 제57권6호
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• pp.985-993
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• 2008

This paper proposes a new DFIG(Doubly-Fed Induction Generator) system using matrix converter, which is very effectively used for interconnecting the wind power system to the power grid. The operation of proposed system was verified by computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was conformed by experimental works with a laboratory scaled-model of wind power system. The laboratory scaled-model was built using a motor-generator set with vector drive system, and a matrix converter with DSP(Digital Signal Processor). The operation of scaled-model was tested by modeling the specific variable-speed wind turbine using the real wind data in order to make the scaled-model simulate the real wind power system as close as possible. The simulation and experimental results confirm that matrix converter can be applied for the DFIG system.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1999년도 학술발표대회 논문집 제18권 2호
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• pp.173-176
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s for video applications. Proposed architecture is designed low power A/D converter that pipelined architecture consists of flash A/D converter. This architecture consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using $0.25{\mu}m$ CMOS technology The SNR is 76.3dB at a sampling rate of 10MHz with 3.9MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}0.5/{\pm}2$ LSB, respectively. The power consumption is 13mW at 10Msample/s.