• Transactions of the Society of Information Storage Systems
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• v.1 no.1
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• pp.23-28
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• 2005

This paper investigates the effects of disk thickness and Pemto slider on PES(position error signal) for high TPI(track per inch) drives above 150kTPI at early stage of their development. In order to reduce the disk flutter which becomes a dominant contributor to the TMR, the thicker disks with both 63 and 69mi1 have been used. Also, PES of a Pemto slider with thinner thickness than Pico slider has been estimated to decrease the conversion factor of disk motion in axial direction to head off-track motion. A frequency-domain PES estimation and prediction tool has been developed via measurement of disk flutter and HSA(head stack assembly) forced vibration. It has been validated by the measured PES in drive level. Based on the model and measurement of disk flutter, PES of a drive with the thicker disk and Pemto slider is predicted and their impact is investigated.

• 한국신재생에너지학회:학술대회논문집
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• 2008.10a
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• pp.94-97
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• 2008

In this paper, A Digital Voltage Mode Controller is designed for the Photovoltaic power converter applications. The designed Digital Voltage Mode Controller is derived analytically from the continuous time small signal model of the boost converter. Due to the small signal model based derivations of the control law, the designed control method can be applicable to K-factor Approach method and bilinear transformation. In order to show the usefulness of a designed controller, and the simulation results are verified.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.409-410
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• 2007

In this paper, we propose a new method for overlap and add synthesis using phase shaping factor in a sinusoidal synthesis method of speech signal, which improves continuity and SNR(Signal Noise Ratio) efficiency of synthesized speech.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.141-143
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• 1998

A new small-signal model for the controlled on-time boost Power factor correction (PFC) circuit is Presented. The proposed small-signal model is valid up to high frequencies ever 1kHz. IF to remove the low-frequency ripple from the output a 120Hz notch filter is used the proposed model can be used for the control design of the PFC circuit to improve the dynamics of the output voltage. The accuracy of the model is confirmed by comparing the experimental results with the simulational result.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.19 no.39
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• pp.243-254
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• 1996

In this study, a model and an analysis method for parameter design is presented a linear relation between the input signal and the ideal value of a performance characteristic. Furthermore, There presented a new performance measure, expected quality loss after adjustment, which is proved to be equivalent to Taguchi's SN ratio approximately. On the basis of this, a two-step optimization procedure is proposed for parameter design considering the signal factor and the quality characteristics with continuous variable. Proposed procedure and Taguchi two-stage procedure are compared.

• Journal of the Optical Society of Korea
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• v.16 no.4
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• pp.401-408
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• 2012

The amplitude error of phase modulator used in closed-loop fiber optic gyroscope has occurred by the temperature dependency of the electro-optic coefficient, and also can be due to the square-wave dither signal which is generally applied for eliminating the deadzone. This error can cause bias drift and scale factor error. This paper analyzes the temperature dependency of the modulation amplitude and the relationship with the scale factor of the gyroscope, and deals with an amplitude control method. The error calculation logic considering the dither signal is implemented on the signal processing module. The result of experiments from a prototype gyroscope shows the effect of the modulation amplitude control and a considerable improvement on performances.

• Journal of Life Science
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• v.12 no.4
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• pp.477-482
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• 2002

As a biological model system for the production of an active antibacterial peptide, we have attempted the expression and secretion of insect defensin in Saccharomyces cerevisiae. Nucleotide sequences encoding mature defensin composed of 40 amino acids were fused in frame with promoter and signal sequence of Saccharomyces diastaticus glucoamylase, and mating factor $\alpha$ l[MF $\alpha$1] prosequence. The host strain, S. cerevisiae 2805 was transformed with the resulting plasmid, pSMFll The secretion of functional defensin was confirmed by growth inhibition zone assay using Micrococcus luteus as a test organism. Insect defensin was secreted to the culture supernatant in biologically active form by glucoamylase signal sequence and mating factor $\alpha$1 prosequence. Most of antibacterial activity was detected in the culture supernatant. Defensin was also active against Staphylococcus aureus and Listeria monocytogenes.

• The Korean Journal of Zoology
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• v.33 no.3
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• pp.266-275
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• 1990

c-raf protein kinase, a kind of oncogene, is a cytopiasmic serine / threonine-specific protein and is activated by mitogenic or oncogenic signals. The strncture and functions of c-raf protein kinase are considered very similar to those of protein kinase C. Using immunocytochemical approach, the time course of singal transduction of c-raf protein kinase in EC-4 cell was examined with 12-0-tetradecanoylphorbol-13-acetate (TPA) as tumor promotor and plateletderived growth factor (PDGF) as mitogenic factor. Immunoreactive c-raf was initially bound to the perinuclear membrane and then moved into the nucleus. The effect of the long-term treatment with TPA or PDGF was taken place down regulation at different time point. These results indicate that TPA and PDGF give rise to the translocation of c-raf protein kinase through the two different pathways.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.262-267
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• 2003

At process of production according to development of accumulation degree of semi-conductor element, because functional mistake examination time required increases, is becoming big obstacle factor in cost-cutting. Studied pattern generator that generate pattern and address that is bundle enemy to process these controversial point effectively.