• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.182-188
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• 2004

We demonstrate a $2.1\;{\times}\;1.0\;{\times}\;0.1cm^3$ sized compact transmitter using LTCC System-in-Package (SiP) technology for 60GHz-band wireless communication applications. For low-attenuation characteristics and resonance suppression of the SiP, we have proposed and demonstrated a coplanar double wire-bond transition and novel CPW-to-stripline transition integrating air-cavities as well as novel air-cavities embedded CPW line. The fabricated transmitter achieves an output of 13dBm at a RF frequency of 62GHz, an IF frequency of 2.4GHz, and a LO frequency of 59.6GHz. The up-conversion gain is 11dB, while the LO signal is suppressed with the image rejection mixer below -21.4dBc, and the image and spurious signals are also suppressed below -31dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.59-65
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• 2008

We have proposed a UHF/HF multi-band RFID reader, and have implemented it into a system in a package(SiP). The proposed SiP RFID reader has been designed to support both for EPCgloabal Class1 Generation2 protocol of UHF band, and 13.56MHz RFID protocols of ISO14443 A/B type, and ISO15693 standards. The operating mode is controlled by embedded RISC core, and the mode can be selected by users. The area of implemented SiP is $40mm{\times}40mm$ with 4 metal layers. The implemented reader SiP operates at single supply voltage of 3.3V. The maximum current consumption is 210mA. The operating distances are 5cm for 13.56MHz modes, and 20cm for UHF mode.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.12
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• pp.2228-2233
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• 2008

This research paper aims to establish a test process of the AFE SiP chip. It measured the sensitivity, current consumption and power consumption both on the evaluation socket board and Catalyst load board. As a result, the sensitivity became deteriorated with an average of 0.2[dBm] at the channel 62 only, the current consumption increased to an average of 0.57[mA] and the power consumption increased to an average of 1.76[mW], But all characteristics incomes the tolerance of the measurement, it also keeps almost the same level. Therefore this design of the test process improved a valid design.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.31-34
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• 2016

System In Package (SiP) is getting popular and momentum for the recent wearable, IoT and connectivity application apart from mobile phone. This is driven by market demands of cost competitive, lighter and smaller/thinner and higher performance. As one of many semiconducting assembly products, Leadframe product has been widely used for low cost solution, light/ small and thin form factor. But It has not been applied for SiP although Leadframe product has many advantages in cost, size and reliability performance. SiP is mostly based on laminate substrate and technically difficult on Leadframe substrate because of a limitation in SMT performance. In this paper, Leadframe based SiP product has been evaluated about key technical challenges in SMT performance and electrical shield technology. Mostly Leadframe is considered not available to apply EMI shield because of tie-bar around package edge. In order to overcome two major challenges, connection bars were deployed properly for SMT pad to pad and additional back-side etching was implemented after molding process to achieve electrical isolation from outer shield coating. This product was confirmed assembly workability as well as reliability.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.9 s.112
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• pp.883-889
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• 2006

In this paper, parasitic resonance modes generated in a conductor backed coplanar wave guide(CBCPW) and stripline band pass filter(BPF) and the oscillation phenomena of a 40 GHz power amplifier module(PAM) are analyzed and several methods to suppress them are presented for low-temperature co-fired ceramic(LTCC) based millimeter-wave RF System-in-Package(SiP) applications. Parasitic rectangular wave guide(RWG) modes of the CBCPW structure are completely suppressed in the operation frequency band by decreasing the distance between its vias and by increasing the mode frequency. In the stripline structure, RWG resonance modes are clearly eliminated by removing some vias facing each other and by placing them diagonally. In the case of the 40 GHz PAM, in order to reduce a cross talk due to radiation that is generated from interconnection discontinuities, high isolation structures such as embedded DC bas lines and CPW signal lines are used and then the oscillated PAM is improved.