• 한국결정성장학회지
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• 제31권4호
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• pp.149-153
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• 2021

ε-Ga₂O₃ 박막은 금속 유기 화학 기상 증착법(MOCVD)에 의해 4H-SiC 기판에 성장되었으며, 결정성은 성장 조건에 따라 평가되었다. ε-Ga₂O₃의 최적 조건은 665℃의 성장 온도와 200 sccm의 산소 유량에서 성장한 것으로 나타났다. hexagonal 핵이 합쳐지면서 2차원으로 성장되었고, hexagonal 핵의 배열 방향은 기판의 결정 방향과 밀접한 관련이 있었다. 그러나 ε-Ga₂O₃의 결정 구조는 hexagonal이 아닌 orthorhombic 구조를 가짐을 확인하였다. 결정상 전이는 열처리에 의해 수행되었다. 그리고 상 전이된 β-Ga₂O₃ 박막과 비교하기 위해 4H-SiC에서 β-Ga₂O₃ 박막을 바로 성장하였다. 상 전이된 β-Ga₂O₃ 박막은 바로 성장한 것보다 더 나은 결정성을 보여주었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• 전기전자학회논문지
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• 제22권1호
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• pp.180-184
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• 2018

산화갈륨 ($Ga_2O_3$)과 탄화규소 (SiC)는 넓은 밴드 갭 ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV)과 높은 임계전압을 갖는 물질로서 높은 항복 전압을 허용한다. 수직 DMOSFET 수평구조에 비해 높은 항복전압 특성을 갖기 때문에 고전압 전력소자에 많이 적용되는 구조이다. 본 연구에서는 2차원 소자 시뮬레이션 (2D-Simulation)을 사용하여 $Ga_2O_3$와 4H-SiC 수직 DMOSFET의 구조를 설계하였으며, 항복전압과 저항이 갖는 trade-off에 관한 파라미터를 분석하여 최적화 설계하였다. 그 결과, 제안된 4H-SiC와 $Ga_2O_3$ 수직 DMOSFET구조는 각각 ~1380 V 및 ~1420 V의 항복 전압을 가지며, 낮은 게이트 전압에서의 $Ga_2O_3-DMOSFET$이 보다 낮은 온-저항을 갖고 있지만, 게이트 전압이 높으면 4H-SiC-DMOSFET가 보다 낮은 온-저항을 갖을 수 있음을 확인하였다. 따라서 적절한 구조와 gate 전압 rating에 따라 소자 구조 및 gate dielectric등에 대한 심화 연구가 요구될 것으로 판단된다.

• Korean Chemical Engineering Research
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• 제49권3호
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• pp.357-360
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• 2011

플라즈마 원자층증착 방법을 이용하여 질소를 도핑한 산화아연 나노박막을 Si(111) 기판에 제조하였다. $Zn(C_{2}H_{5})_{2}$, $O_{2}$ 및 $N_{2}$을 사용하여 rf 파워 세기를 50-300 W로 변화시키면서 N-doped ZnO 박막을 제조하였다. 박막의 구조적 광학적 전기적 특성을 각각 XRD, PL, Hall 효과를 측정하여 분석하였다. 플라즈마 rf 파워가 증가함에 따라 ZnO 나노 박막 내의 질소(N) 함유 농도가 높아지고, p형 ZnO의 특성을 보였다.

• 한국전기전자재료학회논문지
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• 제31권6호
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• pp.362-366
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• 2018

Silicon carbide is widely used in power semiconductor devices owing to its high energy gap. In particular, Schottky barrier diode (SBD) and PiN diodes fabricated on 4H-SiC wafers are being applied to various fields such as power devices. The characteristics of SBD and PiN diodes can be extracted from C-V and I-V characteristics. The measured Schottky barrier height (SBH) was 1.23 eV in the temperature range of 298~473 K, and the average ideal factor is 1.17. The results show that the device with the Schottky contact is characterized by the theory of thermal emission. As the temperature increases, the parameters are changed and the Vth is shifted to lower voltages.

• 한국결정성장학회지
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• 제30권3호
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• pp.96-102
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• 2020

본 논문에서는 6H-SiC (0001) 기판 위에 AlN 에피층을 혼합 소스 수소화물 기상 에피택시 방법에 의해 성장하였다. 시간당 5 nm의 성장률로 0.5 ㎛ 두께의 AlN 에피층을 얻었다. FE-SEM과 EDS 결과를 통해 6H-SiC (0001) 기판 위에 성장된 AlN 에피층 표면을 조사하였다. HR-XRD와 계산식을 통해 전위 밀도를 예측하였다. 1.4 × 10⁹ cm^-2의 나사 전위 밀도와 3.8 × 10⁹ cm^-2의 칼날 전위 밀도를 가지는 우수한 결정질의 AlN 에피층을 확인하였다. 혼합소스 HVP E 방법에 의해 성장된 6H-SiC 기판 위의 AlN 에피층은 전력소자 등에 응용이 가능할 것으로 판단된다.

• 전기전자학회논문지
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• 제22권2호
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• pp.427-431
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• 2018

본 논문에서는 최근 전력반도체 산업에서 활용되어지는 와이드밴드갭 반도체 중에 하나인 $Ga_2O_3$를 이용한 에피웨이퍼 성장에 관련되어 서술하였다. GaN 성장시 활용되어지는 HVPE법을 이용하여 Sn이 도핑된 $Ga_2O_3$ 기판웨이퍼에 평균 $5.3{\mu}m$ 두께로 성장시켰다. 일반적으로 화합물반도체의 에피 두께가 $5{\mu}m$일 경우 SiC의 경우 600V 전력반도체소자를 제작할 수 있으며, $Ga_2O_3$ 에피웨이퍼의 경우에는 1000V이상의 전력소자를 제작할 수 있다. 성장된 에피웨이퍼의 J-V 측정 결과 $2.9-7.7m{\Omega}{\cdot}cm^2$의 온저항을 얻을 수 있었으며, 역방향의 경우 상당히 높은 전압에서도 누설전류가 거의 없음을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제37권2호
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• pp.133-140
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• 2024

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• Transactions on Electrical and Electronic Materials
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• 제18권3호
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• pp.141-143
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• 2017

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.