• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.101-102
• /
• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.1
• /
• pp.101-105
• /
• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• Journal of Sensor Science and Technology
• /
• v.18 no.5
• /
• pp.349-352
• /
• 2009

This paper describes the fabrication and characteristics of micro heaters built on AlN($0.1{\mu}m$)/3C-SiC($1{\mu}m$) suspended membranes by surface micromachining technology. In this work, 3C-SiC and AlN films are used for high temperature environments. Pt thin film was used as micro heaters and temperature sensor materials. The resistance of temperature sensor and the power consumption of micro heaters were measured and calculated. The heater is designed for operating temperature up to about $800^{\circ}C$ and can be operated at about $500^{\circ}C$ with a power of 312 mW. The thermal coefficient of the resistance(TCR) of fabricated Pt resistance of temperature detector(RTD)'s is 3174.64 ppm/$^{\circ}C$. A thermal distribution measured by IR thermovision is uniform on the membrane surface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.9
• /
• pp.916-923
• /
• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.387-390
• /
• 2002

This paper presents deposition and characterizations of microcrystalline silicon(${\mu}$c-Si:H) films prepared by hot wire chemical vapor deposition at substrate temperature below 300$^{\circ}C$. The SiH$_4$ concentration[F(SiH$_4$)/F(SiH$_4$).+(H$_2$)] is critical parameter for the formation of Si films with microcrystalline phase. At 6% of silane concentration, deposited intrinsic ${\mu}$c-Si:H films shows sufficiently low dark conductivity and high photo sensitivity for solar cell applications. P-type ${\mu}$c-S:H films deposited by Hot-Wire CVD also shows good electrical properties by varying the rate of B$_2$H$\_$6/ to SiH$_4$ gas. The solar cells with structure of Al/nip ${\mu}$c-Si:H/TCO/g1ass was fabricated with single chamber Hot-Wire CVD. About 3% solar efficiency was obtained and applicability of HWCVD for thin film solar cells was proven in this research.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.131-131
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.697-705
• /
• 2014

A single chip Programmable AC to DC Power Converter, consisting of wide band gap SiC MOSFET and SiC diodes, has been proposed which converts high frequency ac voltage to a conditioned dc output voltage at user defined given power level. The converter has high conversion efficiency because of negligible reverse recovery current in SiC diode and SiC MOSFET. High frequency operation reduces the need of bigger size inductor. Lead inductors are enough to maintain current continuity. A complete electrical analysis, die area estimation and thermal analysis of the converter has been presented. It has been found that settling time and peak overshoot voltage across the device has reduced significantly when SiC devices are used with respect to Si devices. Reduction in peak overshoot also increases the converter efficiency. The total package substrate dimension of the converter circuit is only $5mm{\times}5mm$. Thermal analysis performed in the paper shows that these devices would be very useful for use as miniaturized power converters for load currents of up to 5-7 amp, keeping the package thermal conductivity limitation in mind. The converter is ideal for voltage requirements for sub-5 V level power supplies for high temperatures and space electronics systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.589-592
• /
• 1999

This paper describes direct $\mu$C-Si/CaF$_2$/glass thin film growth by RPCVD system in a low temperature for thin film transistor (TFT), photovoltaic devices. and sensor applications. Experimental factors in a low temperature direct $\mu$ c-Si film growth are presented in terms of deposition parameters: SiH$_4$/H$_2$ ratio, chamber total pressure, substrate temperature, rf power, and CaF$_2$ buffer layer. The structural and electrical properties of the deposited films were studied by means of Raman spectroscopy, I-V, L-I-V, X-ray diffraction analysis and SEM. we obtain a crystalline volume fraction of 61%, preferential growth of (111) and (220) direction, and photosensitivity of 124. We achieved the improvement of crystallinity and electrical property by using the buffer layers of CaF$_2$ film.

• Proceedings of the KIEE Conference
• /
• 2003.07c
• /
• pp.1592-1594
• /
• 2003

This paper presents the deposition and characterization of microcrystalline silicon(${\mu}c$-Si:H) films by HWCVD(Hot-wire Chemical Vapor Deposition) method at low substrate($300^{\circ}C$). The filament temperature, pressure and $SiH_4$ concentration were determined to be a critical parameter for the deposition of poly-Si films. Series A was deposited under the conditions of $1380^{\circ}C$(Tf), 100 mTorr and $2{\sim}10%\{SC:SiH_4/(SiH_4+H_2)\}$ for 60 min. Series B was deposited under the conditions of $1400{\sim}1450^{\circ}(T_f)$, 30 mTorr and $2{\sim}12%$(SC) for 60 min. The physical characteristics were measured by Raman and FTIR spectroscopy, dark and photoconductivity measurements under AM1.5 illumination.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.2
• /
• pp.236-239
• /
• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.