• Proceedings of the KWS Conference
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• 1999.10a
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• pp.247-250
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• 1999

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.75-78
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• 2000

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.11a
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• pp.48-48
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• 2002

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.27.1-27.1
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• 2011

The recent extensive research of one-dimensional (1D) nanostructures such as nanowires (NWs) and nanotubes (NTs) has been the driving force to fabricate new kinds of nanoscale devices in electronics, optics and bioengineering. We attempt to produce silicon oxide nanowires (SiOxNWs) in a simple way without complicate deposition process, gaseous Si containing precursors, or starting material of $SiO_2$. Nickel (Ni) nanoparticles (NPs) were applied on Si wafer and thermally treated in a furnace. The temperature in the furnace was kept in the ranges between 900 and $1,100^{\circ}C$ and a mixture of nitrogen ($N_2$) and hydrogen ($H_2$) flowed through the furnace. The SiOxNWs had widths ranging from 100 to 200 nm with length extending up to ~10 ${\mu}m$ and their structure was amorphous. Ni NPs were acted as catalysts. Since there were no other Si materials introduced into the furnace, the Si wafer was the only Si sources for the growth of SiOxNWs. When the Si wafer with deposition of Ni NPs was heated, the liquid Ni-Si alloy droplets were formed. The droplets as the nucleation sites induce an initiation of the growth of SiOxNWs and absorb oxygen easily. As the droplets became supersaturated, the SiOxNWs were grown, by the reaction between Si and O and continuously dissolving Si and O onto NPs. Photoluminescence (PL) showed that blue emission spectrum was centered at the wavelength of 450 nm (2.76 eV). The details of growth mechanism of SiOxNWs and the effect of Ni NPs on the formation of SiOxNWs will be presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.5
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• pp.216-220
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• 2010

Ni-Fe alloys have various applications such as thin film inductor, thin film transformer, magnetic head's shield case, etc. Magnetic properties of Ni-Fe thin films depend on the process parameters such as thickness, contents, deposition rate, substrates, etc. In this study, NiFe films with a thickness of about 150nm were deposited on Si(100) wafer and $SiO_2$/Si(100) substrate at room temperature by a DC magnetron co-sputtering using Fe and Ni targets. Their phase formation and magnetic properties as a function of annealing temperature were investigated with XRD, FE-SEM and VSM. The assputtered films have BCC structure. With increasing annealing temperature, NiFe thin film for $SiO_2$/Si(100) substrate transformed completely from BCC to FCC phase above $500^{\circ}C$, but some BCC phase remained above $500^{\circ}C$ on Si(100) wafer. For samples annealed at $450^{\circ}C$, squareness ratio of NiFe thin film shows peak value and its saturation magnetization is around 0.0118 emu, which means that the optimum annealing temperature of NiFe thin film seems to be $450^{\circ}C$. The saturation magnetization of films decreased rapidly above the annealing temperature of $500^{\circ}C$ due to phase transformation from BCC to FCC phase.

• Journal of Sensor Science and Technology
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• v.9 no.2
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• pp.134-140
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• 2000

Si wafer direct bonding(SDB) technology is very attractive for both Si-on-insulator(SOI) electronic devices and MEMS applications. This paper presents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration and applied pressure. The bonding strength was evaluated by tensile strength method. A bond characteristic on the interface was analyzed by using FT-IR, and surface roughness according to HF concentration was analyzed by AFM. Si-F bonds on Si surface after HF pre-treatment are replaced by Si-OH during a DI water rinse. Consequently, hydrophobic wafer was bonded by hydrogen bonding of Si-OH$\cdots$(HOH$\cdots$HOH$\cdots$HOH)$\cdots$OH-Si. The pre-bonding strength depends on the HF pre-treatment condition before pre-bonding. (Min : $2.4kgf/cm^2{\sim}$Max : $14.9kgf/cm^2$)

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.6
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• pp.479-485
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• 2002

We have investigated the effects of various wafers cleaning on glass/Si bonding using 4 inch Pyrex glass wafers and 4 inch silicon wafers. The various wafer cleaning methods were examined; SPM(sulfuric-peroxide mixture, $H_2SO_4:H_2O_2$ = 4 : 1, $120^{\circ}C$), RCA(company name, $NH_4OH:H_2O_2:H_2O$ = 1 : 1 : 5, $80^{\circ}C$), and combinations of those. The best room temperature bonding result was achieved when wafers were cleaned by SPM followed by RCA cleaning. The minimum increase in surface roughness measured by AFM(atomic force microscope) confirmed such results. During successive heat treatments, the bonding strength was improved with increased annealing temperatures up to $400^{\circ}C$, but debonding was observed at $450^{\circ}C$. The difference in thermal expansion coefficients between glass and Si wafer led debonding. When annealed at fixed temperatures(300 and $400^{\circ}C$), bonding strength was enhanced until 28 hours, but then decreased for further anneal. To find the cause of decrease in bonding strength in excessively long annealing time, the ion distribution at Si surface was investigated using SIMS(secondary ion mass spectrometry). tons such as sodium, which had been existed only in glass before annealing, were found at Si surface for long annealed samples. Decrease in bonding strength can be caused by the diffused sodium ions to pass the glass/si interface. Therefore, maximum bonding strength can be achieved when the cleaning procedure and the ion concentrations at interface are optimized in glass/Si wafer direct bonding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.360-361
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• 2005

Rapid progress in IC fabrication technology has strong demand in polishing of silicon wafer to meet the tight specification of nanotopography and surface roughness. One of the important issues in Si CMP is the stabilization of polishing pad. If a polishing pad is not stabilized before main Si wafer polishing process, good polishing result can not be expected. Therefore, new pad must be subjected into break-in process using dummy wafers for a certain period of time to enhance its performance. After the break-in process, the main Si wafer polishing process must be performed. In this study, the characteristics of break-in process were investigated in Si wafer polishing. Viscoelastic behavior, temperature variation of pad and friction were measured to evaluate the break-in phenomenon. Also, it is found that the characteristic of the break-in seems to be related to viscoelastic behavior of pad.