• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.23-28
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• 2009

Si 기판의 캐비티 형성이 불필요한 웨이퍼-레벨 MEMS capping 공정을 연구하였다. 4인치 Si 웨이퍼에 Ni 캡을 전기도금으로 형성하고 Ni 캡 rim을 Si 하부기판의 Cu rim에 에폭시 본딩한 후, SnBi debonding 층을 이용하여 상부기판을 Ni 캡 구조물로부터 debonding 하였다. 진공증착법으로 형성한 SnBi debonding 층은 Bi와 Sn 사이의 심한 증기압 차이에 의해 Bi/Sn의 2층 구조로 이루어져 있었다. SnBi 증착 층을 $150^{\circ}C$에서 15초 이상 유지시에는 Sn과 Bi 사이의 상호 확산에 의해 eutectic 상과 Bi-rich $\beta$상으로 이루어진 SnBi 합금이 형성되었다. $150^{\circ}C$에서 유지시 SnBi의 용융에 의해 Si 기판과 Ni 캡 구조물 사이의 debonding이 가능하였다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.216-216
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• 2012

The purpose of this work is to investigate a back surface field (BSF) on variety wafer resistivity for industrial crystalline silicon solar cells. As pointed out in this manuscript, doping a crucible grown Cz Si ingot with Ga offers a sure way of eliminating the light induced degradation (LID) because the LID defect is composed of B and O complex. However, the low segregation coefficient of Ga in Si causes a much wider resistivity variation along the Ga doped Cz Si ingot. Because of the resistivity variation the Cz Si wafer from different locations has different performance as know. In the light of B doped wafer, we made wider resistivity in Si ingot; we investigated the how resistivities work on the solar cells performance as a BSF quality.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.478-478
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• 2010

대기압 플라즈마 공정은 진공 플라즈마 공정에 비해 장치의 경제성 및 규모면에서 많은 장점을 갖고 있어 대기압 공정에 대한 연구가 필요하다. 본 연구는 대기압 DC Arc Plasmatron을 이용하여 기체의 유량, 전류, plasmatron과 Si wafer 간의 거리를 변화시켜 이에 대한 Si wafer에 식각률(etching rate)을 확인하고 최적화 하였다. Ar은 2000sccm, $CF_4$는 50, 100sccm, 그리고 $O_2$는 0~1000sccm의 유량에 변화를 주었고 전류는 50A, 70A에서 식각하였다. 분석을 위해 Si wafer를 SEM(scanning electron microscope) 측정을 하였고, 그 결과 전류는 70A에서 기체 유량은 $CF_4$는 100sccm, $O_2$는 500sccm 일 때 식각률이 높게 나타났다. 그리고 전류와 유량을 위와 같은 조건에서 Plasmatron과 Si wafer 간의 거리를 5mm~15mm 변화를 주었을 때 Si wafer에 식각률을 측정해 본 결과 거리가 5mm일 때 식각률이 가장 높음을 확인 할 수 있었다. 아울러 거리를 변화시켰을 때가 유량이나 전압을 변화시킨 것 보다 식각률의 변화가 큰 경향을 보임을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• 한국세라믹학회지
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• 제34권7호
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• pp.699-702
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• 1997

The cross sectional image of thin oxide failure of MOS device could be observed by Emission Microscope and Focused Ion Beam at the weak point. The oxide failures in low electric field was associated with the presence of a particle or abnormal pattern. The failures occuring at medium field are related to a pit of Si substrate. The pits could be originated from the microdefects of Cz Si wafer.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1997년도 Proceedings of the 12th KACG Technical Meeting and the 4th Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.261-263
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• 1997

6H-SiC single crystals were successfully grown by the self-designed sublimation apparatus and the optimum growth condition was established. The grown SiC crystals were about 33mm in diameter and 10mm in length. Carrier concentration and doping type of undopped 6H-SiC wafer grown by sublimation method were 1016∼1017/㎤ and n-type Crystallinity of grown 6H-SiC wafer was better than of Acheson seed by data of Raman spectroscopy and Double Crystal XRD. We continue to characterize the grown 6H-SiC wafer in more detail and so we will grow the high-quality 6H-SiC single crystal wafer.

• 전자통신동향분석
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• 제36권3호
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• pp.23-33
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• 2021

Two main technologies of III-V/Si laser diode for optical communication, direct epitaxial growth, and wafer bonding were studied. Until now, the wafer bonding has been vigorously studied and seems promising for the ideal III-V/Si laser. However, the wafer bonding process is still complicated and has a limit of mass production. The development of a concise and innovative integration method for silicon photonics is urgent. In the future, the demand for high-speed data processing and energy saving, as well as ultra-high density integration, will increase. Therefore, the study for the hetero-junction, which is that the III-V compound semiconductor is directly grown on Si semiconductor can overcome the current limitations and may be the goal for the ideal III-V/Si laser diode.