• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.11
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• pp.1765-1771
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• 2010

In the case of micro.electro-mechanical system (MEMS) devices, the quality of punched via hole is one of the most important factors governing the performance of the device. The common features that affect the laser micromachining of via holes drilled by using Nd:$YVO_4$ laser are described, and efficient optimization methods to measure them are presented. The analysis methods involving an orthogonal array, analysis of variance (ANOVA), and response surface optimization are employed to determine the main effects and to determine the optimal laser process parameters. The significant laser process parameters were identified and their effects on the quality of via holes were studied. Finally, an experiment in which the optimal levels of the laser process parameters were used was carried out to demonstrate the effectiveness of the optimization method.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.19-24
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• 2019

In this study, the Ag nano-dots structure was applied to the textured wafer surface to improve the light trapping effect of crystalline silicon solar cell. The Ag nano-dots structure was formed by the annealing of Ag thin film. Ag thin film deposition was performed using a thermal evaporator. The effect of light trapping was compared and analyzed through light reflectance measurements. The optimization process of the Ag nano-dots structure was made by varying the thickness of Ag thin film, the annealing temperature and time. The thickness of Ag thin films was in the range of 5 ~ 20 nm. The annealing temperature was in the range of 450~650℃ and the annealing time was in the range of 30 ~ 60 minutes. As a result, the light reflectance of 10 nm Ag thin film annealed at 650℃ for 30 minutes showed the lowest value of about 9.67%. This is a value that is about 3.37% lower than the light reflectance of the sample that has undergone only the texturing process. Finally, the change of the light reflectance by the HF treatment of the sample on which the Ag nano-dots structure was formed was investigated. The HF treatment time was in the range of 0 ~ 120 seconds. As a result, the light reflectance decreased by about 0.41% due to the HF treatment for 75 seconds.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.80-90
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• 1994

The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).

• Journal of IKEEE
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• v.19 no.4
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• pp.535-540
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• 2015

A microstrip gas chamber (MSGC), applied to digital radiography system, was designed and constructed. The microstrip electrodes were fabricated with Chrome(Cr.). by photolithography process on Silicon(Si) wafer and glass substrate. The width of anode and cathode electrodes was $10{\mu}m$, and $290{\mu}m$, respectively. The distance of the electrodes was $100{\mu}m$, and the active area was $50{\times}50mm^2$. And the number of anode was 80. The microstrip electrodes were damaged when discharges occurred over the 600 V of anode voltage. As the result of experiments. It detected the typical output signals of the pulse width, 20 ns, under the condition that the detecting gas was Ar(90%) + $CH_4$(10%), X-ray tube voltage was 42 kV, and tube current was 1 mA.

• Journal of the Korean Magnetics Society
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• v.9 no.6
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• pp.291-295
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• 1999

$NiFe/Co/Al_2O_3/Co/IrMn$ tunneling junctions were grown on (100)Si wafer and their spin-valve tunneling magnetoresistance (TMR) was studied. The tunneling junctions were grown by using a 5-gun RF/DC magnetron sputter. $Al_2O_3$ barrier layer was formed by exposing Al layer to oxygen atmosphere at 6$0^{\circ}C$ for 72 hours. Strong exchange coupling interaction is observed between the ferromagnetic Co and the antiferromagnetic IrMn of Co/IrMn bilayer when IrMn is 100$\AA$ thick. $NiFe(183\;{\AA})/Co(17\;{\AA})/Al_2O_3(16\;{\AA})/Co(100\;{\AA})/IrMn(100\;{\AA})$ tunneling junction shows best TMR ratio of about 10% in the applied magnetic field range of $\pm$20 Oe. The TMR ratio is improved about 23% and electrical resistance is decreased about 34% when annealed at 200 $^{\circ}C$ for 1 hour in magnetic field of 330 Oe, parallel to the bottom electrode. With increasing the active area of junction the TMR ratio increases while electrical resistance decreases.

• Korean Journal of Materials Research
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• v.19 no.4
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• pp.224-227
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• 2009

Nanofabrication is an essential process throughout industry. Technologies that produce general nanofabrication, such as e-beam lithography, dip-pen lithography, DUV lithography, immersion lithography, and laser interference lithography, have drawbacks including complicated processes, low throughput, and high costs, whereas nano-transfer printing (nTP) is inexpensive, simple, and can produce patterns on non-plane substrates and multilayer structures. In general nTP, the coherency of gold-deposited stamps is strengthened by using SAM treatment on substrates, so the gold patterns are transferred from stamps to substrates. However, it is hard to apply to transfer other metallic materials, and the existing nTP process requires a complicated surface treatment. Therefore, it is necessary to simplify the nTP technology to obtain an easy and simple method for fabricating metal patterns. In this paper, asnTP process with poly vinyl alcohol (PVA) mold was proposed without any chemical treatment. At first, a PVA mold was duplicated from the master mold. Then, a Mo layer, with a thickness of 20 nm, was deposited on the PVA mold. The Mo deposited PVA mold was put on the Si wafer substrate, and nTP process progressed. After the nTP process, the PVA mold was removed using DI water, and transferred Mo nano patterns were characterized by a Scanning electron micrograph (SEM) and Energy Dispersive spectroscopy (EDS).

• Macromolecular Research
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• v.12 no.1
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• pp.78-84
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• 2004

Advanced epoxy molding compounds (EMCs) should be considered to alleviate the thermal stress problems caused by low thermal conductivity and high elastic modulus of an EMC and by the mismatch of the coefficient of thermal expansion (CTE) between an EMC and the Si-wafer. Though A1N has some advantages, such as high thermal conductivity and mechanical strength, an A1N-filled EMC could not be applied to commercial products because of its low fluidity and high modules. To solve this problem, we used 2-$\mu\textrm{m}$ fused silica, which has low porosity and spherical shape, as a small size filler in the binary mixture of fillers. When the composition of the silica in the binary filler system reached 0.3, the fluidity of EMC was improved more than twofold and the mechanical strength was improved 1.5 times, relative to the 23-$\mu\textrm{m}$ A1N-filled EMC. In addition, the values of the elastic modules and the dielectric constant were reduced to 90％, although the thermal conductivity of EMC was reduced from 4.3 to 2.5 W/m-K, when compared with the 23-$\mu\textrm{m}$ A1N-filled EMC. Thus, the A1N/silica (7/3)-filled EMC effectively meets the requirements of an advanced electronic packaging material for commercial products, such as high thermal conductivity (more than 2 W/m-K), high fluidity, low elastic modules, low dielectric constant, and low CTE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.240-244
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• 2011

The high cost of crystalline silicon solar cells has been considered as one of the major obstacles to their terrestrial applications. Spin on doping (SOD) is presented as a useful process for the manufacturing of low cost solar cells. Phosphorus (P509) was used as an n-type emitters of solar cells. N-type emitters were formed on p-type EFG ribbon Si wafers by using a SOD at different spin speed (1,000~4,000 rpm), diffusion temperatures ($800^{\circ}C{\sim}950^{\circ}C$), and diffusion time (5~30 min) in $N_2+O_2$ atmosphere. With optimum condition, we were able to achieve cell efficiency of 14.1%.

• Tribology and Lubricants
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• v.21 no.3
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• pp.107-113
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• 2005

Micro/nano adhesion and friction properties of self-assembled monolayers (SAMs) with different head- and end-group were experimentally studied according to the coating methods. Various kinds of SAM having different spacer chains (C10 and C18), head-group and end-group were deposited onto Si-wafer by dipping and chemical vapour deposition (CVD) methods under atmospheric pressure, where the deposited SAM resulted in the hydrophobic nature. The adhesion and friction properties between tip and SAM surfaces under nano scale applied load were measured using an atomic force microscope (AFM) and also those under micro scale applied load were measured using a ball-on-flat type micro-tribotester. Surface roughness and water contact angles were measured with SPM (scanning probe microscope) and contact anglemeter respectively. Results showed that water contact angles of SAMs with the end-group of fluorine show higher relatively than those of hydrogen. SAMs with the end-group of fluorine show lower nano-adhesion but higher micro/nanofriction than those with hydrogen. Water contact angles of SAMs coated by CVD method show high values compared to those by dipping method. SAMs coated by CVD method show the increase of nano-adhesion but the decrease of nano-friction. Nano-adhesion and friction mechanism of SAMs with different end-group was proposed in a view of size of fluorocarbon molecule.