• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• 한국전기전자재료학회논문지
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• 제16권8호
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• pp.657-662
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• 2003

This paper presents a new fabrication method of selective SiGe epitaxial growth at 650 $^{\circ}C$ on (100) silicon wafer with oxide patterns by reduced pressure chemical vapor deposition. The new method is characterized by a cyclic process, which is composed of two parts: initially, selective SiGe epitaxy layer is grown on exposed bare silicon during a short incubation time by SiH$_4$/GeH$_4$/HCl/H$_2$system and followed etching step is achieved to remove the SiGe nuclei on oxide by HCl/H$_2$system without source gas flow. As a result, we noted that the addition of HCl serves not only to reduce the growth rate on bare Si, but also to suppress the nucleation on SiO$_2$. In addition, we confirmed that the incubation period is regenerated after etching step, so it is possible to grow thick SiGe epitaxial layer sustaining the selectivity. The effect of the addition of HCl and dopants incorporation was investigated.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• 한국진공학회지
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• 제11권1호
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• pp.16-21
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• 2002

$Si_2H_6$가스를 이용한 LPCVD내에서의 실리콘의 선택적 에피텍시 성장을 $1000^{\circ}C$ 이하의 초청정 분위기하의 저온에서 수행하였다. HCI 첨가없이 초청정 공정으로 인한 양질의 에피텍시 Si층이 균일하게 얻어 졌으며, $SiO_2$위에 증착된 실리콘의 잠복기를 발견할 수 있었다. 단결정위의 에피텍시 층은 산화물 층위 보다 더 두껍게 증착되었다. 산소첨가로 잠복기가 20~30초간 증가하였다. 증착된 박막의 절단면과 표면 형상은 SEM으로 관찰되었으며, XRD를 통해 막질을 평가하였다.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• 대한전자공학회논문지
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• 제22권1호
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• pp.34-40
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• 1985

시스뎀 압력이 1.0 기압[대기압 공정]일 경우와 0.1 기압(감압 공정)일 경우에 대해, SiH2Cl2를 사용했을 때의 에퍼택셜층 및 폴리실리콘의 성장 현상과 HCI을 사용했을 때의 이것들의 에칭 현상을 조사하였다. 실험적으로 구한 성장 속도 및 에칭 속도에 대한 식들로부터 Sih2Cl2와 HCI을 혼합하여 사용할 경우에 대한 선화적 에퍼택시가 가능한 공정 조건이 예측되었다. 그 결과, 선택적 에퍼택셜 성장 영역이 감압 공정에서는 실험 범위내에서 존재하였지만 대기압 공정에서는 존재하지 않는 것으로 나타났다. 이 것은 대기압과 감압에서의 성장 속도 및 에칭 속도가 차이가 나기 때문에 기인하는 것이다.

• 한국재료학회지
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• 제12권5호
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• pp.363-368
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• 2002

we proposed the use of $Si_2H_ 6/H_2$ chemistry for selective silicon epitaxy growth by low-pressure chemical vapor deposition(LPCVD) in the temperature range $600~710^{\circ}C$ under an ultraclean environment. As a result of ultraclean processing, an incubation period of Si deposition only on $SiO_2$ was found, and low temperature epitaxy selective deposition on Si was achieved without addition of HCI. Total gas flow rate and deposition pressure were 16.6sccm and 3.5mtorr, respectively. In this condition, we selectively obtained high-quality epitaxial Si layers of the 350~1050$\AA$ thickness. In older to extend the selectivity, we kept high pressure $H_2$ environment without $Si_2H_6$ gas for few minutes after first incubation period and then we conformed the existence of second incubation period.

• 대한전자공학회논문지
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• 제23권6호
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• pp.801-806
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• 1986

The effect of SiH2Cl2 -HCl gas on the growth rate of epitaxial layer is studied. The temperature, pressure and gas mixing ratio of SiH2Cl2 and HCl are varied to study the growth rate dependence and selective Si epitaxy. The P-n junction diode is fabricated on the epitaxial layer and electrical characteristics are examined. Also, using selective Si epitaxy, a possibility of thin dielectric isolation process, that gives an independent isolation width on the mask dimension, is examined.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1025-1027
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• 1995

SEG(Selective Epitaxial Growth) and ELO(Epitaxial Lateral Growth) of Silicon offer new opportunities in the fabrication of MEMS(Micro Electro-Mechanical Systems) structures. SEG of silicon enables the stacking of junctions in addition to those resulting from the standard bipolar process and this properly was utilized for the fabrication of an improved-performance color sensor. When the crystalline growth takes place through the seed windows and proceeds over the dielectric, after reaching the surface, it form an ELO silicon layer and this ELO-Si can be modified into various structures for MEMS application such as cantilevers, beams, diaphragms.

• 반도체디스플레이기술학회지
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• 제15권1호
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• pp.41-46
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• 2016

In this study, gas flow and temperature distribution in the multi-wafer planetary CVD reactor for the Si epitaxial growth were analyzed. Although the structure of the reactor was simplified as the first step of the study, the three-dimensional analysis was performed taking all these considerations of the revolution of the susceptor and the rotation of satellites into account. From the analyses, a reasonable velocity field and temperature field were obtained. However, it was found that analyses including the upper structure of the reactor were required in order to obtain more realistic temperature results. DCS mole fraction above the satellite surface and the susceptor surface without satellite was compared in order to check the gas species mixing. We found that satellite rotation helped gases to mix in the reactor.