• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.4-4
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• 2004

• Journal of the Mineralogical Society of Korea
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• v.21 no.1
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• pp.27-35
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• 2008

Characterization of mineralogy and nanocrystals of ingredient materials of $Lumilite^{(R)}$ used for water treatment was made using optical microscopy, XRD, SEM, FTIR, and XRF analyses. Constituent minerals identified by XRD and microscope are clinoptilolite, illite, quartz, and albite, characterized by dense and fine texture. The cross section of nanocrystals with the size $70{$\sim}100\;nm$ is generally round or subround. Numerous spheroids with few nanometers in diameter are extensively formed on the surface of nanocrystals. Bulk chemistry is $SiO_2$ $74.22{\sim}75.65\;wt.%$, $Al_2O_3$ $13.25{\sim}13.72\;wt.%$, CaO $4.23{\sim}5.15\;wt.%$, with other major elements being minimal. When heated to $700^{\circ}C$, the crystal structure was mostly destroyed, though it persisted to $500^{\circ}C$. It is likely that high capacity and applications of $Lumilite^{(R)}$ for water treatment are originated from its structural properties such as development of nanocrystals and various tiny pores.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.93-93
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• 2003

Photoluminescence(PL) properties of Silicon nanocrystals (nc-Si) as a function of temperature is reported to consider the mechanism of PL. Nc-Si has been made by $Si^+$ ion-implantation into thermal $SiO_2$ and subsequent annealing. And after gold had been diffused at the same samples above, the resultant PL spectra has been compared to the PL spectra from the non-gold doped nc-Si. PL peak energy variation from nc-Si is same with the variation of energy bandgap of bulk silicon as temperature changes from 6 K to room temperature. This result may mean nc-Si is still indirect transition material like bulk silicon. Gold doped nc-Si reveals short peak wavelength of PL spectrum than gold undoped one. PL peak shift through gold doing process shows clearly the PL mechanism is not from defect or interface states. PL intensity increases from 6K to a certain temperature and then decrease to room temperature. This characteristic with temperature shows that phonon have a role for the luminescence as theory explains that electron and hole can be recombined radiatively by phonon's assist in nc-Si, which is almost impossible in bulk silicon. Therefore luminescence is observed in nc-Si constructed less than a few of unit cell and the peak energy of luminescence can be higher than the bulk bandgap energy by the bandgap widening effect occurs in nanostructure.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.78-78
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• 2009

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1341-1342
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• 2006

Electrical characteristics of field-effect thin film transistors (TFTs) with p-channels of CdTe/CdHgTe core-shell nanocrystals are investigated in this paper. For the fabrication of bottom- and top-gate TFTs, CdTe/CrHgTe nanocrystals synthesized by colloidal method are first dispersed on oxidized p+ Si substrates by spin-coating, the dispersed nanoparticles are sintered at $150^{\circ}C$ to form the channels for the TFTs, and $Al_{2}O_{3}$ layers are deposited on the channels. A representative bottom-gate field-effect TFT with a bottom-gate $SiO_2$ layer exhibits a mobility of $0.21cm^2$/ Vs and an Ion/Ioff ratio of $1.5{\times}10^2$ and a representative top-gate field-effect TFT with a top-gate $Al_{2}O_{3}$ layer provides a field-effect mobility of $0.026cm^2$/ Vs and an Ion/Ioff ratio of $2.5{\times}10^2$. $Al_{2}O_{3}$ was deposited for passivation of CdTe/CdHgTe core-shell nanocrystal layer, resulting in enhanced hole mobility, Ior/Ioff ratio by 0.25, $3{\times}10^3$, respectively. The CdTe/CdHgTe nanocrystal-based TFTs with bottom- and top gate geometries are compared in this paper.

• Proceedings of the Optical Society of Korea Conference
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• 2009.10a
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• pp.353-354
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.222-222
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• 2009