• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.725-730
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• 1996

The key process in silicon surface micromachining is the selective etching of a sacrificial layer to release the silicon microstructure. The newly developed anhydrous HF/$CH_3$OH gas phase etching of TEOS (teraethylorthosilicate) sacrificial layers onto the polysilicon and the nitride substrates was employed to release the polysilicon microstructures. A residual product after TEOS etching onto the nitride substrate was observed on the surface, since a SiOxNy layer is formed on the TEOS/nitride interface. The polysilicon microstructures are stuck to the underlying substrate because SiOxNy layer does not vaporize. We found that the only sacrificial etching without any residual product and stiction is TEOS etching onto the polysilicon substrate.

• Journal of the Korean Vacuum Society
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• v.21 no.4
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• pp.199-204
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• 2012

$SF_6$ gas is widely used for dry etching process of semiconductor and display fabrication process. But $SF_6$ gas is considered for typical greenhouse gas for global warming. So it is necessary to research relating to $SF_6$ alternatives reducing greenhouse effect in semiconductor and display. $C_3F_6$ gas is one of the promising candidates for it. We studied about etch characteristics by performing Reactive Ion Etching process of dry etching and reduced gas element exhausted on etching process using absorbent Zeolite 5A. $Si_3N_4$ thin film was deposited to 500 nm with Plasma Enhanced Chemical Vapor Deposition and we performed Reactive Ion Etching process after patterning through photolithography process. It was observed that the etch rate and the etched surface of $Si_3N_4$ thin film with Scanning Electron Microscope pictures. And we measured and compared the exhausted gas before and after the absorbent using Gas Chromatograph-Mass Spectrophotometry.

• Bulletin of the Korean Chemical Society
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• v.34 no.11
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• pp.3451-3455
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• 2013

Single-crystalline silicon nanowires (SiNWs) were fabricated by using an electroless metal-assisted etching of bulk silicon wafers with silver nanoparticles obtained by wet electroless deposition. The etching of SiNWs is based on sequential treatment in aqueous solutions of silver nitrate followed by hydrofluoric acid and hydrogen peroxide. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the Si substrate were produced. Free-standing SiNWs were then obtained using ultrasono-method in toluene. Alkyl-derivatized SiNWs were prepared to prevent the aggregation of SiNWs and obtained from the reaction of SiNWs and dodecene via hydrosilylation. Optical characterizations of SiNWs were achieved by FT-IR spectroscopy and indicated that the surface of SiNWs is terminated with hydrogen for fresh SiNWs and with dodecyl group for dodecyl-derivatized SiNWs, respectively. The main structures of dodecyl-derivatized SiNWs are wires and rods and their thicknesses of rods and wire are typically 150-250 and 10-20 nm, respectively. The morphology and chemical state of dodecyl-derivatized SiNWs are characterized by scanning electron microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.206-211
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• 2015

We investigated the formation of a nanopyramidal structure and fabricated nanotextured Si solar cells using an Ag metal-assisted chemical etching process. The nanopyramidal structure was formed on a Si flat surface and the nanotexturing process was performed on the p-type microtextured Si surface. The nanostructural formation shows a transition from nanopits and nanopores to nanowires with etching time. The nanotextured surfaces also showed the photoluminescence spectra with an enhanced intensity in the wavelength range of 1,100~1,250 nm. The photoreflectance of the nanotextured Si solar cells was strongly reduced in the wavelength range of 337~596 nm. However, the quantum efficiency is decreased in the nanotextured samples due to the increased nanosurface recombination. The nanotexturing process provides a better p-n junction impedance of the nanotextured cells, resulting in an enhanced shunt resistance and fill factor which in turn renders the possibility of the increased conversion efficiency.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.49.1-49.1
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• 2010

The particle generation during the plasma enhanced process is highly considered as serious problem in the semiconductor manufacturing industry. The material for the plasma processing chamber requires the plasma etching characteristics which are homogeneously etched surface and low plasma etching depth for preventing particulate contamination and high durability. We found that the materials without grain boundaries can prevent the particle generation. Therefore, the amorphous material with the low plasma etching rate may be the best candidate for the plasma processing chamber instead of the polycrystalline materials such as yttria and alumina. Three glasses based on $SiO_2$ and $Al_2O_3$ were prepared with various rare-earth elements (Gd, Y and La) which are same content in the glass. The glasses were plasma etched in the same condition and their plasma etching rate was compared including reference materials such as Si-wafer, quartz, yttria and alumina. The mechanical and thermal properties of the glasses were highly related with cationic field strength (CFS) of the rare-earth elements. We assumed that the plasma etching resistance may highly contributed by the thermal properties of the fluorine byproducts generated during the plasma exposure and it is expected that the Gd containing glass may have the highest plasma etching resistance due to the highest sublimation temperature of $GdF_3$ among three rare-earth elements (Gd, Y and La). However, it is found that the plasma etching results is highly related with the mechanical property of the glasses which indicates the cationic field strength. From the result, we conclude that the glass structure should be analyzed and the plasma etching test should be conducted with different condition in the future to understand the plasma etching behavior of the glasses perfectly.

• ETRI Journal
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• v.27 no.3
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.328-333
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• 2023

This study experimentally verified the etch rate of the SiO₂ sacrificial layer etching process with a single etch hole using vapor-phase hydrogen fluoride (VHF) etching. To fabricate small-sized polysilicon etch holes, both circular and triangular pattern masks were employed. Etch holes were fabricated in the polysilicon thin film on the SiO₂ sacrificial layer, and VHF etching was performed to release the polysilicon thin film. The lateral etch rate was measured for varying etch hole sizes and sacrificial layer thicknesses. Based on the measured results, we obtained an approximate equation for the etch rate as a function of the etch hole size and sacrificial layer thickness. The etch rates obtained in this study can be utilized to minimize structural damage caused by incomplete or excessive etching in sacrificial layer processes. In addition, the results of this study provide insights for optimizing sacrificial layer etching and properly designing the size and spacing of the etch holes. In the future, further research will be conducted to explore the formation of structures using chemical vapor deposition (CVD) processes to simultaneously seal etch hole and prevent adhesion owing to polysilicon film vibration.

• Journal of Electrical Engineering and Technology
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• v.3 no.2
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• pp.271-275
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• 2008

The MAM(Megasonic Agitated Module) has been fabricated for improving the characteristics of wet etching. The characteristics of the MAM are investigated during the wet etching with and without megasonic agitation in this paper. The adoption of the MAM has improved the characteristics of wet etching, such as the etch rate, etch uniformity, and surface roughness. Especially, the etching uniformity on the entire wafer was less than ${\pm}1%$ in both cases of Si and glass. Generally, the initial root-mean-square roughness($R_{rms}$) of the single crystal silicon was 0.23nm. Roughnesses of 566nm and 66nm have been achieved with magnetic stirring and ultrasonic agitation, respectively, by some researchers. In this paper, the roughness of the etched Si surface is less than 60 nm. Wet etching of silicon with megasonic agitation can maintain nearly the original surface roughness during etching. The results verified that megasonic agitation is an effective way to improve etching characteristics of the etch rate, etch uniformity, and surface roughness and that the developed micromachining system is suitable for the fabrication of devices with complex structures.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.91-96
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• 1987

Plasma etching can obtain less damaged etch surface than reactive ion etching. This study was performed to get anisotropic etching characteristics of Si using two step etching technique with C2CIF5 and SF6 gas mixture. The results show that the etch rate and aspect ratio of silicon was increased with increment of SF6 contents. The bulging phenomenon on trench side wall in the plasma one-step etching technique was eliminated by the two step etching technique. The anisotropy was decreased from 12(at 120m Torr) to 2.2(at 400m Torr) with increasing the chamber pressure. At the low rf power (350 watts) anisotrpy of silicon was obtained 7 lower than that of high rf power (650 watts. A:~9). In Summary we obtained anisotropic etching profiles of silicon with e 6\ulcornerm depth by using the plasma two-step etching technique.