• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.232-232
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• 2006

SiC single crystal Ingots were prepared onto different seed material using sublimation PVT techniques and then their crystal quality was systematically compared. In this study, the conventional SiC seed material and the new SiC seed material with an inserted SiC epitaxial layer on a seed surface were used as a seed for SiC bulk growth. The inserted epitaxial layer was grown by a sublimation epitaxy method called the CST with a low growth rate of $2{\mu}m/h$ N-type 2"-SIC single crystals exhibiting the polytype of 6H-SiC were successfully fabricated and carrier concentration levels of below $10^{17}/cm^3$ were determined from the absorption spectrum and Hall measurements. The slightly higher growth rate and carrier concentration were obtained in SiC single crystal Ingot grown on new SiC Seed materials with the inserted epitaxial layer on the seed surface, maintaining the high quality.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.657-662
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• 2003

This paper presents a new fabrication method of selective SiGe epitaxial growth at 650 $^{\circ}C$ on (100) silicon wafer with oxide patterns by reduced pressure chemical vapor deposition. The new method is characterized by a cyclic process, which is composed of two parts: initially, selective SiGe epitaxy layer is grown on exposed bare silicon during a short incubation time by SiH$_4$/GeH$_4$/HCl/H$_2$system and followed etching step is achieved to remove the SiGe nuclei on oxide by HCl/H$_2$system without source gas flow. As a result, we noted that the addition of HCl serves not only to reduce the growth rate on bare Si, but also to suppress the nucleation on SiO$_2$. In addition, we confirmed that the incubation period is regenerated after etching step, so it is possible to grow thick SiGe epitaxial layer sustaining the selectivity. The effect of the addition of HCl and dopants incorporation was investigated.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.100-100
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• 2003

본 연구에서는 Si에 Mn을 첨가한 Si$_{l-x}$Mn$_{x}$ 박막의 전기적 및 자기적 특성을 조사하였다. Si$_{l-x}$Mn$_{x}$ 박막은 MBE(Molecular Beam Epitaxy)를 이용하여 native oxide층을 제거하지 않은 (100)Si wafer 위에 성장하였다. Substrate 온도는 50$0^{\circ}C$로 하였으며, 첨가한 Mn 농도는 20%에서부터 80%까지였다. 전기적 특성은 Hall, 4-point probe를 통하여 측정하였고, 자기적 특성은 VSM, FMR, SQUID을 이용하여 측정하였다. 상 분석은 XRD, TEM을 이용하여 관찰하였다 Si$_{l-x}$Mn$_{x}$ 박막은 Hall 측정 결과 상온에서 P-type carrier를 가지며, 비저항은 반도체 영역인 7.6$\times$$10^{-4}$~4.2$\times$$10^{-2}$(ohm-cm)의 값을 가진다. 상온 VSM, 측정결과 Mn의 양이 52% 첨가 시 포화 자화 값이 가장 높은 40emu/cc를 가지며, Mn의 양이 증가할수록 포화 자화 값이 증가하다 다시 감소하는 경향을 가진다. FMR, SQUID 측정에서도 이러한 경향을 확인할 수 있었다 특히, SQUID 분석 결과 두 개 이상의 자성 상이 존재하는 것을 관찰할 수 있었다. XRD, TEM 관찰결과, Si$_{l-x}$Mn$_{x}$은 poly crystal로 성장하였으며, Mn 농도에 따라 여러 상들이 관찰되었다.따라 여러 상들이 관찰되었다.

• Korean Journal of Materials Research
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• v.13 no.2
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• pp.88-93
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• 2003

Co/Ti bilayer structure in Co salicide process helps to the improvement of device speed by lowering contact resistance due to the epitaxial growth of $CoSi_2$layers. We investigated the epitaxial growth and interfacial mass transport of $CoSi_2$layers formed from $150 \AA$-Co/Ti structure with two step rapid thermal annealing (RTA). The thicknesses of Ti layers were varied from 20 $\AA$ to 100 $\AA$. After we confirmed the appropriate deposition of Ti film even below $100\AA$-thick, we investigated the cross sectional microstructure, surface roughness, eptiaxial growth, and mass transportation of$ CoSi_2$films formed from various Ti thickness with a cross sectional transmission electron microscopy XTEM), scanning probe microscopy (SPM), X-ray diffractometery (XRD), and Auger electron depth profiling, respectively. We found that all Ti interlayer led to$ CoSi_2$epitaxial growth, while $20 \AA$-thick Ti caused imperfect epitaxy. Ti interlayer also caused Co-Ti-Si compounds on top of $CoSi_2$, which were very hard to remove selectively. Our result implied that we need to employ appropriate Ti thickness to enhance the epitaxial growth as well as to lessen Co-Ti-Si compound formation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of IKEEE
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• v.13 no.4
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• pp.23-27
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• 2009

Ohmic contact formation and etching processes for the fabrication of MBE (molecular beam epitaxy) grown GaSb-based p-channel HEMT devices on Si substrate have been studied. Firstly, mesa etching process was established for device isolation, based on both HF-based wet etching and ICP-based dry etching. Ohmic contact process for the source and drain formation was also studied based on Ge/Au/Ni/Au metal stack, which resulted in a contact resistance as low as $0.683\;{\Omega}mm$ with RTA at $320^{\circ}C$ for 60s. Finally, for gate formation of HEMT device, gate recess process was studied based on AZ300 developer and citric acid-based wet etching, in which the latter turned out to have high etching selectivity between GaSb and AlGaSb layers that were used as the cap and the barrier of the device, respectively.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.445-449
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• 1999

We studied the properties of the InAs epitaxial layers grown of (100)-oriented GaAs ($2^{\circ}$tilted toward[011]) by molecular beam epitaxy. From DCX (double-crystal x0ray), the better crystal quality was shown in InAs epitaxial layers on about 2500$\AA$ GaAs epitaxial layers on GaAs, we obtained the high mobility of InAs epitaxy in As/In BEP ratio (1.2~2.0) from Hall effect measurement. The electron mobility increased as electron concentration increases, until Si cell temperature $960^{\circ}C$$(N_D=2.21\times10^{-17}\textrm{cm}^{-3})$. The mobility decreases as the Si cell temperature increases, at the temperature over $960^{\circ}C$. We obtained the high mobility (1.10$\times$104cm2/V.s) at Si electron concentration of $N_D=2.21\times10^{-17}\textrm{cm}^{-3}$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.17 no.5
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• pp.179-186
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• 2007

Single crystal $CdGa_2Se_4$ layers were grown on a thoroughly etched semi-insulating GaAs(100) substrate at $420^{\circ}C$ with the hot wall epitaxy(HWE) system by evaporating the polycrystal source of $CdGa_2Se_4$ at $630^{\circ}C$. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction(DCXD). The carrier density and mobility of single crystal $CdGa_2Se_4$ thin films measured with Hall effect by van der Pauw method are $8.27{\times}10^{17}cm^{-3},\;345cm^2/V{\cdot}s$ at 293 K, respectively. The photocurrent and the absorption spectra of $CdGa_2Se_4/SI$(Semi-Insulated) GaAs(100) are measured ranging from 293 K to 10 K. The temperature dependence of the energy band gap of the $CdGa_2Se_4$ obtained from the absorption spectra was well described by the Varshni's relation $E_g(T)=2.6400eV-(7.721{\times}10^{-4}eV/K)T^2/(T+399K)$. Using the photocurrent spectra and the Hopfield quasicubic model, the crystal field energy(${\Delta}cr$) and the spin-orbit splitting energy(${\Delta}so$) far the valence band of the $CdGa_2Se_4$ have been estimated to be 106.5 meV and 418.9 meV at 10 K, respectively. The three photocurrent peaks observed at 10 K are ascribed to the $A_{1^-},\;B_{1^-},\;and\;C_{11}-exciton$ peaks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.