• 제목/요약/키워드: Si∥$SiO_2$/${Si_3}{N_4}$∥Si 기판쌍

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선형열처리를 이용한 Si(100)/Si$_3$N$_4$∥Si (100) 기판쌍의 직접접합 (Direct bonding of Si(100)/Si$_3$N$_4$∥Si (100) wafers using fast linear annealing method)

  • 이영민;송오성;이상연
    • 한국재료학회지
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    • 제11권5호
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    • pp.427-430
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    • 2001
  • 절연 특성이 기존의 SiO$_2$ 보다 우수한 500 두께의 SiN$_4$층을 두 단결정 실리콘사이의 절연막질로 채택하고 직접접합시켜 직경 10cm의 Si(100) /500 -Si$_3$N$_4$/Si (100) 기판쌍을 제조하였다. p-type (100) 실리콘기판을 친수성, 소수성을 갖도록 습식방법으로 세척한 두 그룹의 시편들을 준비하였다. 기판전면에 LPCVD로 500 $\AA$ 두께의 Si$_3$N$_4$∥Si(100) 기판을 성장시키고 실리론 기판과 고청정상태에서 가접시킨 후, 선형열원의 이동속도를 0.1mm/s로 고정시키고 선형 입열량을 400~1125w 범위에서 변화시키면서 직접접합을 실시하였다. 접합된 기판은 적외선 카메라로 계면 접합면적을 확인하고 razor blade creek opening 측정법으로 세정 방법에 따른 각 기판쌍 그들의 접합강도를 확인하였다. 접합강도가 측정된 기판쌍은 high resolution transmission electron microscopy (HRTEM )을 사용하여 수직단면 미세구조를 조사하였다. 입열량의 증가에 따라 두 그를 모두 접합율은 큰 유의차 없이 765% 정도로, 소수성 처리가 된 기판쌍의 접합강도는 1577mJ/$m^2$가지 선형적으로 증가하였으나, 친수성 처리가 된 기판쌍은 주어진 실험 범위에서 입열량의 증가에 따라 큰 변화 없이 2000mj/$m^2$이상의 접합 강도를 보였다 친수성 처리가 된 기판쌍의 수직단면 미세구조를 고분해능 투과전자현미경으로 각인한 결과 모든 시편의 실리콘과 Si$_3$N$_4$사이에 25 $\AA$ 정도의 SiO$_2$ 자연산화막이 존재하여 중간충 역할을 함으로서 기판접합강도를 향상시키는 것으로 판단되었다.

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사점굽힘시험법을 이용한 이종절연막 (Si/SiO2||Si3N4/Si) SOI 기판쌍의 접합강도 연구 (Direct Bonded (Si/SiO2∥Si3N4/Si) SIO Wafer Pairs with Four-point Bending)

  • 이상현;송오성
    • 한국재료학회지
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    • 제12권6호
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    • pp.508-512
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    • 2002
  • $2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

전기로를 이용한 Si || SiO2/Si3N4 || Si 이종기판쌍의 직접접합 (Direct Bonding of Si || SiO2/Si3N4 || Si Wafer Pairs With a Furnace)

  • 이상현;이상돈;서태윤;송오성
    • 한국재료학회지
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    • 제12권2호
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    • pp.117-120
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    • 2002
  • We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

직접접합 실리콘/실리콘질화막//실리콘산화막/실리콘 기판쌍의 선형가열에 의한 보이드 결함 제거 (Eliminating Voids in Direct Bonded Si/Si3N4‖SiO2/Si Wafer Pairs Using a Fast Linear Annealing)

  • 정영순;송오성;김득중;주영철
    • 한국재료학회지
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    • 제14권5호
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    • pp.315-321
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    • 2004
  • The void evolution in direct bonding process of $Si/Si_3$$N_4$$SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

열처리 방법에 따른 이종절연층 실리콘 기판쌍의 직접접합 (Direct Bonding of Heterogeneous Insulator Silicon Pairs using Various Annealing Method)

  • 송오성;이기영
    • 한국전기전자재료학회논문지
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    • 제16권10호
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    • pp.859-864
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    • 2003
  • We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.