• 한국안전학회지
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• 제8권4호
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• pp.95-100
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• 1993

In power transistor switching circuit have shunt snubber(dv/dt limiting capacitor) and series snubber (di/dt limiting inductor). The shunt snubber is used to reduce the turn-off switching loss and the series snubber is used to reduce the turn-on switching loss. Design procedures are derived for selecting the capacitance, inductor and resistance to limit the peak voltage and current values. The action of snubber is analyzed and applied to the design for safety PWM inverter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• KIEE International Transactions on Power Engineering
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• 제5A권2호
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• pp.152-158
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• 2005

This paper describes a reactive optimal power flow incorporating margin enhancement constraints. Margin sensitivity at a steady-state voltage instability point is calculated using invariant space parametric sensitivity, and it can provide valuable information for selection of effective control parameters. However, the weakest buses in neighboring regions have high margin sensitivities within a certain range. Hence, the control determination using only the sensitivity information might cause violation of operational limits of the base operating point, at which the control is applied to enhance voltage stability margin in the direction of parameter increase. This paper applies an interior point method (IPM) to solve the optimal power flow formulation with the margin enhancement constraints, and shunt capacitances are mainly considered as control variables. In addition, nonlinearity of margin enhancement with respect to control of shunt capacitance is considered for speed-up control determination in the numerical example using the IEEE 118-bus test system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.977-978
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• 2007

The phase angle which is mainly depend on time constant $\tau$ of the calculable 10 A and 0.1 ${\Omega}ac/dc$ resistor has been analysed. The low values of resistors are usually inductive and time constant $\tau$ very large compare to high values of resistors. The numerical analysis has been shown that the time constant $\tau$ becomes zero when introduce the compensation capacitance geometrically to the resistive coil with proper dimension. As a result a very low phase angle can be achieved within the realizable dimensions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.181-184
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• 2001

A coplanar waveguide(CPW) on a dielectric substrate consists of a center strip conductor with semi-infinite ground planes on either side. This type of waveguide offers several advantages over microstrip line. It facilitates easy shunt as well as series mounting of active and passive devices. It eliminates the need for wraparound and via holes, and it has a low radiation loss. These, as well as several other advantages, make CPW ideally suited for microwave integrated circuit applications. However, very little information is available in the literature on models for CPW discontinuities. This lack of sufficient discontinuity models for CPW has limited the application of CPW in microwave circuit design. We presented for the characteristics of coplanar waveguide open end capacitance and series gap capacitance. Measurements by utilizing the resonance method were made and the experimental data confirmed the validity of theories. The relationships between the CPW capacitances and the physical dimensions were studied.

• 한국세라믹학회지
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• 제55권3호
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• pp.244-260
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• 2018

Issues in the electrical characterization of semiconducting photoanodes in a photoelectrochemical (PEC) cell, such as the cell geometry dependence, scan rate dependence in DC measurements, and the frequency dependence in AC measurements, are addressed, using the example of a $TiO_2$ photoanode. Contrary to conventional constant phase element (CPE) modeling, the capacitive behavior associated with Mott-Schottky (MS) response was successfully modeled by a Havriliak-Negami (HN) capacitance function-which allowed the determination of frequency-independent Schottky capacitance parameters to be explained by a trapping mechanism. Additional polarization can be successfully described by the parallel connection of a Bisquert transmission line (TL) model for the diffusion-recombination process in the nanostructured $TiO_2$ electrode. Instead of shunt CPEs generally employed for the non-ideal TL feature, TL models with ideal shunt capacitors can describe the experimental data in the presence of an infinite-length Warburg element as internal interfacial impedance - a characteristic suggested to be a generic feature of many electrochemical cells. Fully parametrized impedance spectra finally allow in-depth physicochemical interpretations.

• 전기학회논문지
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• 제58권7호
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• pp.1294-1303
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• 2009

This paper presents a new numerical algorithm for fault discrimination and fault location estimation when occur to arcing ground and arcing line to line on transmission lines. The object of this paper is developed from new numerical algorithm to calculate the fault distance and simultaneously to make a distinction between transient and permanent faults. so the first of object for propose algorithm would be distinguish the permanent from the transient faults. This arcing fault discrimination algorithm is used if calculated value of arc voltage amplitude is greater than product of arc voltage gradient and the length of the arc path, which is equal or greater than the flashover length of a suspension insulator string[1-3]. Also, each algorithm is separated from short distance and long distance. This is difference to with/without capacitance between short to long distance. To test the validity of the proposed algorithms, the results of algorithm testing through various computer simulations are given. The test was simulated in EMTP/ATP simulator under a number of scenarios and calculate of algorithm was used to MATLAB.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• 조명전기설비학회논문지
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• 제27권1호
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• pp.99-108
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• 2013

The high-voltage pulse generator is consist of transformers of fundamental wave and harmonic waves, and shunt capacitances. The pulse has the fundamental wave and the harmonic waves that have been increased as a series circuit by the transformers to make high voltage pulse. This paper shows that pulse generator circuit is analyzed using Miller's theorem and network theory(ABCD Matrix) and simulated in frequency and time domain using Matlab program. The output voltage of pulse were obtained to 2.5kHz, 1.8kV. Output pulse voltage increases as $L_m$ increases in low voltage circuit. In high voltage circuit, outer capacitors are related to frequency band pass characteristics.

• 조명전기설비학회논문지
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• 제26권12호
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• pp.80-86
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• 2012

The high-voltage pulse generator is consist of transformers of fundamental wave and harmonic waves, and shunt capacitances. The pulse has the fundamental wave and the harmonic waves that have been increased as a series circuit by the transformers to make high voltage pulse. This paper shows the high-voltage pulse generator simulation using a circuit program with experiment data. In the equivalent circuit, magnetized inductances and loss resistances which affect output voltage, have been obtained. The output capacitor circuits have characteristics of band pass. The output voltages of the pulse width 50% and 25%(PWM) were obtained. The output of the high-voltage pulse generator is 2.5kHz, 1.8kV.