• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1422-1428
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1925-1930
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• 2014

This paper has analyzed the relation of conduction path and subthreshold swing for doping profile in channel of asymmetric double gate(DG) MOSFET. Since the channel size of asymmetric DGMOSFET is greatly small and number of impurity is few, the high doping channel is analyzed. The analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. The conduction path and subthreshold swing are derived from this analytical potential distribution, and those are investigated for variables of doping profile, projected range and standard projected deviation, according to the change of channel length and thickness. As a result, subthreshold swing is reduced when conduction path is approaching to top gate, and that is increased with a decrease of channel length and a increase of channel thickness due to short channel effects.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.98-104
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• 1990

A study of the operation of surface and buried mode PMOSFET's is condusted. Using device with different channel length and channel implant dosage, threshold voltage lowering, transcon-diuctance and subthreshold characteristics of surface mode PMOFET are compared with those of buried mode MPOSFET. From the results, the surface channel device were more resistant to short channel effect than the buried channel device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.225-230
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• 1994

In this paper, we have fabricated short channel MOSFETs with these parameters to verify the validity of process parameters extraction by DTC method. The experimental results of fabricated short channel devices according to the optimal process parameters demonstrate good device characteristics such as good drain current-voltage characteristics, low body effects and threshold voltage of$\leq$+-.1.0V, high punch through and breakdown voltage of$\leq$12V, low subthreshold swing(S.S) values of$\leq$105mV/decade.

• Journal of Digital Contents Society
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• v.7 no.3
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• pp.139-145
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• 2006

Short-range wireless transmission and networking technologies are becoming increasingly important in enabling useful mobile applications. Bluetooth and IEEE 802.11b standards are the most commonly deployed technologies for WPAN and WLAN. This paper investigates the effect of short range wireless channel on the performance of MC-CDMA/BPSK system and Bluetooth GFSK signal transmission in AWGN and Rician fading environments. And we investigate performance degradation due to interference effects in short range wireless channel. We firstly derive a equation for the bit error probability in additive white Gaussian noise depending on MC-CDMA/BPSK signal and GFSK modulation signal parameters according to the Bluetooth RF standard. Then, from this error rate expression we calculate the mean error probability for MC-CDMA/BPSK signal and Bluetooth GFSK signal in Rician fading and interference channel. In particular, the impacts of the Rician fading depth and interference level on the error probability is shown in BER performance figures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2015-2020
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• 2012

The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.205-209
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• 1991

The conventional modeling equations for planar MOSFET can not be directly used for zero or minus junction depth concave MOSFET. In this paper, we suggest a new model which can simulate the electrical characteristics of concave MOSFET. The threshold voltage modeling was achieved using the charge sharing method considering the relative difference of source and drain depletion widths. To analyze the ID-VDS characteristics, the conventional expressions for planar MOSFET were employed with the electrical channel length as an effective channel length and the channel length modulation factor as ${\alpha}$ΔL. By comparing the proposed model with experimental results, we could get reasonably similar curves and we proposed a concave MOSFET conditiion which shows no short channel effect of threshold voltage(V${\gamma}$).

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.243-249
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• 2010

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].